SA1110 Datasheet, PDF (8/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

11.7.3.5 Base Address Update Interrupt Mask (BAM) ...................................... 11–28
11.7.3.6 Error Interrupt Mask (ERM) ................................................................. 11–28
11.7.3.7 Passive/Active Display Select (PAS)................................................... 11–28
11.7.3.8 Big/Little Endian Select (BLE) ............................................................. 11–30
11.7.3.9 Double-Pixel Data (DPD) Pin Mode .................................................... 11–30
11.7.3.10 Palette DMA Request Delay (PDD)..................................................... 11–30
11.7.4 LCD Controller Control Register 1............................................................. 11–33
11.7.4.1 Pixels Per Line (PPL) .......................................................................... 11–33
11.7.4.2 Horizontal Sync Pulse Width (HSW) ................................................... 11–33
11.7.4.3 End-of-Line Pixel Clock Wait Count (ELW) ......................................... 11–33
11.7.4.4 Beginning-of-Line Pixel Clock Wait Count (BLW)................................ 11–34
11.7.5 LCD Controller Control Register 2............................................................. 11–35
11.7.5.1 Lines Per Panel (LPP) ......................................................................... 11–35
11.7.5.2 Vertical Sync Pulse Width (VSW)........................................................ 11–35
11.7.5.3 End-of-Frame Line Clock Wait Count (EFW) ...................................... 11–36
11.7.5.4 Beginning-of-Frame Line Clock Wait Count (BFW)............................. 11–36
11.7.6 LCD Controller Control Register 3............................................................. 11–38
11.7.6.1 Pixel Clock Divider (PCD).................................................................... 11–38
11.7.6.2 AC Bias Pin Frequency (ACB)............................................................. 11–38
11.7.6.3 AC Bias Pin Transitions Per Interrupt (API)......................................... 11–39
11.7.6.4 Vertical Sync Polarity (VSP) ................................................................ 11–39
11.7.6.5 Horizontal Sync Polarity (HSP)............................................................ 11–39
11.7.6.6 Pixel Clock Polarity (PCP) ................................................................... 11–39
11.7.6.7 Output Enable Polarity (OEP).............................................................. 11–40
11.7.7 LCD Controller DMA Registers.................................................................. 11–41
11.7.8 DMA Channel 1 Base Address Register ................................................... 11–42
11.7.9 DMA Channel 1 Current Address Register................................................ 11–43
11.7.10 DMA Channel 2 Base and Current Address Registers.............................. 11–44
11.7.11 LCD Controller Status Register ................................................................. 11–45
11.7.11.1 LCD Disable Done Flag (LDD) (read/write, maskable interrupt) ......... 11–45
11.7.11.2 Base Address Update Flag (BAU) (read-only, maskable interrupt)..... 11–45
11.7.11.3 Bus Error Status (BER) (read/write, maskable interrupt)..................... 11–45
11.7.11.4 AC Bias Count Status (ABC) (read/write, nonmaskable interrupt) ...... 11–46
11.7.11.5 Input FIFO Overrun Lower Panel Status (IOL) (read/write,
maskable interrupt).............................................................................. 11–46
11.7.11.6 Input FIFO Underrun Lower Panel Status (IUL) (read/write,
maskable interrupt).............................................................................. 11–46
11.7.11.7 Input FIFO Overrun Upper Panel Status (IOU) (read/write,
maskable interrupt).............................................................................. 11–46
11.7.11.8 Input FIFO Underrun Upper Panel Status (IUU) (read/write,
maskable interrupt).............................................................................. 11–46
11.7.11.9 Output FIFO Overrun Lower Panel Status (OOL) (read/write,
maskable interrupt).............................................................................. 11–46
11.7.11.10Output FIFO Underrun Lower Panel Status (OUL) (read/write,
maskable interrupt).............................................................................. 11–47
11.7.11.11Output FIFO Overrun Upper Panel Status (OOU) (read/write,
maskable interrupt).............................................................................. 11–47
11.7.11.12Output FIFO Underrun Upper Panel Status (OUU) (read/write,
maskable interrupt).............................................................................. 11–47
11.7.12 LCD Controller Register Locations ............................................................ 11–49
11.7.13 LCD Controller Pin Timing Diagrams ........................................................ 11–50
11.8 Serial Port 0 – USB Device Controller .......................................................... 11–55
11.8.1 USB Operation .......................................................................................... 11–56
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SA-1110 Developer’s Manual