SA1110 Datasheet, PDF (11/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

11.10.10.2Transmit Underrun Status (TUR) (read/write, maskable interrupt) ...11–102
11.10.10.3Receiver Abort Status (RAB) (read/write, nonmaskable interrupt) ...11–102
11.10.10.4Transmit FIFO Service Request Flag (TFS) (read-only,
maskable interrupt) ............................................................................11–103
11.10.10.5Receive FIFO Service Request Flag (RFS) (read-only,
maskable interrupt) ............................................................................11–103
11.10.10.6Framing Error Status (FRE) (read/write, nonmaskable interrupt) .....11–104
11.10.11HSSP Status Register 1 .........................................................................11–105
11.10.11.1Receiver Synchronized Flag (RSY) (read-only, noninterruptible) .....11–105
11.10.11.2Transmitter Busy Flag (TBY) (read-only, noninterruptible) ...............11–105
11.10.11.3Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)..11–105
11.10.11.4Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)......11–105
11.10.11.5End-of-Frame Flag (EOF) (read-only, noninterruptible)....................11–105
11.10.11.6CRC Error Status (CRE) (read-only, noninterruptible)......................11–106
11.10.11.7Receiver Overrun Status (ROR) (read-only, noninterruptible) ..........11–106
11.10.12UART Register Locations .......................................................................11–108
11.10.13HSSP Register Locations .......................................................................11–108
11.11 Serial Port 3 – UART...................................................................................11–109
11.11.1 UART Operation ......................................................................................11–109
11.11.1.1 Frame Format....................................................................................11–110
11.11.1.2 Baud Rate Generation.......................................................................11–110
11.11.1.3 Receive Operation.............................................................................11–110
11.11.1.4 Transmit Operation............................................................................11–111
11.11.1.5 Transmit and Receive FIFOs.............................................................11–111
11.11.1.6 CPU and DMA Register Access Sizes ..............................................11–111
11.11.2 UART Register Definitions.......................................................................11–111
11.11.3 UART Control Register 0 .........................................................................11–112
11.11.3.1 Parity Enable (PE) .............................................................................11–112
11.11.3.2 Odd/Even Parity Select (OES) ..........................................................11–112
11.11.3.3 Stop Bit Select (SBS) ........................................................................11–112
11.11.3.4 Data Size Select (DSS) .....................................................................11–112
11.11.3.5 Sample Clock Enable (SCE) .............................................................11–113
11.11.3.6 Receive Clock Edge Select (RCE) ....................................................11–113
11.11.3.7 Transmit Clock Edge Select (TCE)....................................................11–113
11.11.4 UART Control Registers 1 and 2 .............................................................11–115
11.11.4.1 Baud Rate Divisor (BRD)...................................................................11–115
11.11.5 UART Control Register 3 .........................................................................11–116
11.11.5.1 Receiver Enable (RXE) .....................................................................11–116
11.11.5.2 Transmitter Enable (TXE) ..................................................................11–116
11.11.5.3 Break (BRK) ......................................................................................11–116
11.11.5.4 Receive FIFO Interrupt Enable (RIE) ................................................11–117
11.11.5.5 Transmit FIFO Interrupt Enable (TIE) ................................................11–117
11.11.5.6 Loopback Mode (LBM) ......................................................................11–117
11.11.6 UART Data Register ................................................................................11–118
11.11.7 UART Status Register 0 ..........................................................................11–120
11.11.7.1 Transmit FIFO Service Request Flag (TFS) (read-only,
maskable interrupt) ............................................................................11–120
11.11.7.2 Receive FIFO Service Request Flag (RFS) (read-only,
maskable interrupt)11–120
11.11.7.3 Receiver Idle Status (RID) (read/write, maskable interrupt) ..............11–121
11.11.7.4 Receiver Begin of Break Status (RBB) (read/write,
nonmaskable interrupt) ......................................................................11–121
11.11.7.5 Receiver End of Break Status (REB) (read/write,
SA-1110 Developer’s Manual
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