SA1110 Datasheet, PDF (169/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
Figure 10-20. SMROM Eight-Beat and Two-Beat Timing for 2 M x 16 Bit Organization
(32 Mbit) at Half-Memory Clock Frequency (MDREFR:K0DB2=1)
Memory
Clock
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
RL
CL
2
SDCLK
SDCKE
command
nCS
ACT READ
ACT READ STOP
nSDRAS
nSDCAS
DRA12-0
Row
Col
Row
Col
nWE
nOE
RD/nWR
D
D0 D1 D2 D3 D4 D5 D6 D7
Contents of SMROM/DRAM register fields:
last
time
first
RL=2 cycle SMCNFG:CLO=4 (CL=5 cycle)
MDCAS00=0101 0101 0101 0101 0101 0101 0111 1111(binary)
SMCNFG:RA0=4
MDCAS01=0101 0101 0101 0101 0101 0101 0101 0101(binary)
A6644-02
10.6
PCMCIA Overview
The SA-1110 PCMCIA interface provides controls for one PCMCIA card slot with a PSKTSEL
pin for support of a second slot. This 16-bit host interface supports 8- and 16-bit peripherals and
handles common memory, I/O, and attribute memory accesses. The interface does not support the
PCMCIA DMA protocol. The duration of each access is based on an internally generated clock that
is programmed per address space by fields within the MECR register. Figure 10-21 shows the
memory map for the PCMCIA space.
SA-1110 Developer’s Manual
10-55