SA1110 Datasheet, PDF (193/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.6.2
11.6.3
DMA Operation
The DMA controller provides dynamic context switching between active channels on a demand
basis. A context switch may occur when a channel completes a command or when a particular burst
(portion of a transfer) has been completed. For example, if the FIFO in a particular transmit serial
controller is full and cannot accept more data, that channel may be switched out of the active
context in favor of another channel that is requesting service. An active channel may actually go
idle many times as the device is serviced. Channels are serviced in a fixed priority with channel 0
being the highest and channel 5 being the lowest.
DMA Register List
The following table lists the registers contained within the DMA controller:
Physical Address
Channel 0 Registers
0h B000 0000
0h B000 0004
0h B000 0008
0h B000 000C
0h B000 0010
0h B000 0014
0h B000 0018
0h B000 001C
Channel 1 Registers
0h B000 0020
0h B000 0024
0h B000 0028
0h B000 002C
0h B000 0030
0h B000 0034
0h B000 0038
0h B000 003C
Channel 2 Registers
0h B000 0040
0h B000 0044
0h B000 0048
0h B000 004C
0h B000 0050
0h B000 0054
0h B000 0058
0h B000 005C
Register Name
DMA device address register.
DMA control/status register 0.
Write ones to set.
Write ones to clear.
Read only.
DMA buffer A start address 0.
DMA buffer A transfer count 0.
DMA buffer B start address 0.
DMA buffer B transfer count 0.
DMA device address register 1.
DMA control/status register 1.
Write ones to set.
Write ones to clear.
Read only.
DMA buffer A start address 1.
DMA buffer A transfer count 1.
DMA buffer B start address 1.
DMA buffer B transfer count 1.
DMA device address register 2
DMA control/status register 2.
Write ones to set.
Write ones to clear.
Read only.
DMA buffer A start address 2.
DMA buffer A transfer count 2.
DMA buffer B start address 2.
DMA buffer B transfer count 2.
Symbol
DDAR0
DCSR0
DBSA0
DBTA0
DBSB0
DBTB0
DDAR1
DCSR1
DBSA1
DBTA1
DBSB1
DBTB1
DDAR2
DCSR2
DBSA2
DBTA2
DBSB2
DBTB2
SA-1110 Developer’s Manual
11-13