SA1110 Datasheet, PDF (12/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

nonmaskable interrupt)...................................................................... 11–121
11.11.7.6 Error in FIFO Flag (EIF) (read-only, nonmaskable interrupt)............. 11–121
11.11.8 UART Status Register 1 .......................................................................... 11–123
11.11.8.1 Transmitter Busy Flag (TBY) (read-only, noninterruptible)................ 11–123
11.11.8.2 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible) .. 11–123
11.11.8.3 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible) ...... 11–123
11.11.8.4 Parity Error Flag (PRE) (read-only, noninterruptible) ........................ 11–123
11.11.8.5 Framing Error Flag (FRE) (read-only, noninterruptible)..................... 11–124
11.11.8.6 Receiver Overrun Flag (ROR) (read-only, noninterruptible).............. 11–124
11.11.9 UART Register Locations ........................................................................ 11–126
11.12 Serial Port 4 – MCP / SSP .......................................................................... 11–126
11.12.1 MCP Operation ........................................................................................ 11–127
11.12.1.1 Frame Format.................................................................................... 11–128
11.12.1.2 Audio and Telecom Sample Rates and Data Transfer ...................... 11–129
11.12.1.3 MCP Transmit and Receive FIFO Operation..................................... 11–130
11.12.1.4 Codec Control Register Data Transfer .............................................. 11–131
11.12.1.5 External Clock Operation................................................................... 11–132
11.12.1.6 Alternate SSP Pin Assignment .......................................................... 11–132
11.12.1.7 CPU and DMA Register Access Sizes .............................................. 11–132
11.12.2 MCP Register Definitions ........................................................................ 11–133
11.12.3 MCP Control Register 0........................................................................... 11–133
11.12.3.1 Audio Sample Rate Divisor (ASD)..................................................... 11–133
11.12.3.2 Telecom Sample Rate Divisor (TSD) ................................................ 11–134
11.12.3.3 Multimedia Communications Port Enable (MCE) .............................. 11–135
11.12.3.4 External Clock Select (ECS).............................................................. 11–135
11.12.3.5 A/D Sampling Mode (ADM) ............................................................... 11–135
11.12.3.6 Telecom Transmit FIFO Interrupt Enable (TTE)................................ 11–136
11.12.3.7 Telecom Receive FIFO Interrupt Enable (TRE) ................................ 11–136
11.12.3.8 Audio Transmit FIFO Interrupt Enable (ATE) .................................... 11–136
11.12.3.9 Audio Receive FIFO Interrupt Enable (ARE)..................................... 11–136
11.12.3.10Loopback Mode (LBM) ..................................................................... 11–137
11.12.3.11External Clock Prescaler (ECP)........................................................ 11–137
11.12.4 MCP Control Register 1........................................................................... 11–140
11.12.4.1 Clock Frequency Select (CFS) .......................................................... 11–140
11.12.5 MCP Data Registers ................................................................................ 11–141
11.12.5.1 MCP Data Register 0......................................................................... 11–141
11.12.5.2 MCP Data Register 1......................................................................... 11–142
11.12.5.3 MCP Data Register 2......................................................................... 11–143
11.12.6 MCP Status Register ............................................................................... 11–145
11.12.6.1 Audio Transmit FIFO Service Request Flag (ATS) (read-only,
maskable interrupt)............................................................................ 11–145
11.12.6.2 Audio Receive FIFO Service Request Flag (ARS) (read-only,
maskable interrupt)............................................................................ 11–146
11.12.6.3 Telecom Transmit FIFO Service Request Flag (TTS) (read-only,
maskable interrupt)............................................................................ 11–146
11.12.6.4 Telecom Receive FIFO Service Request Flag (TRS) (read-only,
maskable interrupt)............................................................................ 11–146
11.12.6.5 Audio Transmit FIFO Underrun Status (ATU) (read/write,
nonmaskable interrupt)...................................................................... 11–146
11.12.6.6 Audio Receive FIFO Overrun Status (ARO) (read/write,
nonmaskable interrupt)...................................................................... 11–147
11.12.6.7 Telecom Transmit FIFO Underrun Status (TTU) (read/write,
nonmaskable interrupt)...................................................................... 11–147
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SA-1110 Developer’s Manual