SA1110 Datasheet, PDF (389/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Register Summary
A
This appendix describes all of the Intel^® StrongARM^* SA-1110 Microprocessor (SA-1110)
internal registers.
Physical Address
UDC Registers (Serial Port 0)
0h 8000 0000
0h 8000 0004
0h 8000 0008
0h 8000 000C
0h 8000 0010
0h 8000 0014
0h 8000 0018
0h 8000 001C
0h 8000 0020
0h 8000 0024
0h 8000 0028
0h 8000 002C
0h 8000 0030
UART Registers (Serial Port 1)
0h 8001 0000
0h 8001 0004
0h 8003 0008
0h 8001 000C
0h 8001 0010
0h 8001 0014
0h 8001 0018
0h 8001 001C
0h 8001 0020
0h 8001 0024 – 0h 8001 FFFF
GPCLK Registers (Serial Port 1)
0h 8002 0060
0h 8002 0064
0h 8002 0068
0h 8002 006C
0h 8002 0070
0h 8002 0074
Symbol
Register Name
UDCCR
UDCAR
UDCOMP
UDCIMP
UDCCS0
UDCCS1
UDCCS2
UDCD0
UDCWC
—
UDCDR
—
UDCSR
UDC control register.
UDC address register.
UDC OUT max packet register.
UDC IN max packet register.
UDC endpoint 0 control/status register.
UDC endpoint 1 (out) control/status register.
UDC endpoint 2 (in) control/status register.
UDC endpoint 0 data register.
UDC endpoint 0 write count register.
Reserved.
UDC transmit/receive data register (FIFOs).
Reserved.
UDC status/interrupt register.
UTCR0
UTCR1
UTCR2
UTCR3
—
UTDR
—
UTSR0
UTSR1
—
UART control register 0.
UART control register 1.
UART control register 2.
UART control register 3.
Reserved.
UART data register.
Reserved.
UART status register 0.
UART status register 1.
Reserved.
GPCLKR0
—
—
GPCLKR1
GPCLKR2
—
GPCLK Control Register 0.
GPCLK Control Register 1.
Reserved.
GPCLK Control Register 2.
GPCLK Control Register 3.
Reserved.
SA-1110 Developer’s Manual
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