SA1110 Datasheet, PDF (43/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Instruction Set
4
This section describes the instruction timing for the Intel^® StrongARM^* SA-1110 Microprocessor
(SA-1110).
4.1
Instruction Set
The SA-1110 implements the ARM^* V4 architecture as defined in the ARM Architecture Reference,
28-July-1995, with previously noted options and additions.
4.2
Instruction Timing
Table 4-1.
Table 4-1 lists the instruction timing for the SA-1110. The result delay is the number of cycles that
the next sequential instruction would stall if it used the result as an input. The issue cycles are the
number of cycles that this instruction takes to issue. For most instructions, the result delay is zero
and the issue cycles is one. For load and stores, the timing is for cache hits.
Instruction Timing
Instruction Group
Data processing
Mul or Mul/Add giving 32-bit result
Mul or Mul/Add giving 64-bit result
Load single – write-back of base
Load single – load data zero extended
Load single – load data sign extended
Store single – write-back of base
Load multiple (delay for last register)
Store multiple – write-back of base
Branch or branch and link
MCR
MRC
MSR to control
MRS
Swap
Result Delay
0
1..3
1..3
0
1
2
0
1
0
0
2
1
0
0
2
Issue Cycles
1
1
2
1
1
1
1
MAX
(2, number of registers loaded)
MAX
(2, number of registers loaded)
1
1
1
3
1
2
* Other brands and names are the property of their respective owners.
SA-1110 Developer’s Manual
4-1