SA1110 Datasheet, PDF (247/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
c. Drain the remaining bytes out of the FIFO.
d. Setup the endpoint to get ready for a new packet of data.
7. EndPoint2 Interrupt
a. Check that a complete packet was transmitted.
b. Check for any errors.
c. Setup the endpoint to transmit a new packet of data.
11.8.4 UDC Address Register
Reset
The UDC address register contains a 7-bit field that holds the device address. After a reset of the
UDC core, the value of this register is zero. The CPU writes an address to this register when it
receives a SET_ADDRESS from the USB host controller. It extracts the address assigned to the
UDC from the SET_ADDRESS command and writes the value into the UDC address register. The
new address is not propagated to the rest of the UDC core until the SET_ADDRESS command is
completed with an acknowledged handshake from the UDC.
0h 8000 0004
UDCAR
Read/Write
7
6
5
4
3
2
1
0
Reserved
7-bit Function Address
0
0
0
0
0
0
0
0
Bits
Name
Description
Function address field
6..0
Address
7-bit function address. Reset to all zero.
Reserved.
7
—
Always read zero.
11.8.5
UDC OUT Max Packet Register
The UDC OUT max packet register holds the value of the maximum packet size the UDC core will
accept minus one. This is done in order to accommodate maximum packets of 256 bytes, without
going to a max packet field of more than 8 bits. In order to accept packets up to 256 bytes, a value
of 0xff (255) should be written into the OUT max packet register. At reset the OUT max packet
register contains 0x08, and will therefore accept packets of length 9 bytes or less.
0h 8000 0008
7
6
5
Reset
0
0
0
UDCOMP
4
3
Max Packet Size - 1
0
1
Read/Write
2
1
0
0
0
0
Bits
Name
Description
OUT max packet size.
7..0
OUT MaxP
8-bit field containing the value of the maximum packet size minus one.
SA-1110 Developer’s Manual
11-67