SA1110 Datasheet, PDF (255/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.8.11
UDC Endpoint 0 Write Count Register
The UDC endpoint 0 write count register can be read when a packet has been received by the
endpoint 0 to determine how many bytes to read out of the UDC endpoint 0 data register. When
data is present in the FIFO, this 4-bit field should read between 1 and 8.
Reset
0h 8000 0020
7
6
5
Reserved
0
0
0
UDCWC
4
3
0
0
Read-Only
2
1
0
Write Count
0
0
0
Bits
Name
Description
Endpoint 0 write count (read-only).
3..0
WC
4-bit field representing the number of bytes in the endpoint 0 FIFO.
Reserved.
7..4
—
Always reads zero.
11.8.12
UDC Data Register
The UDC data register (UDCDR) is an 8-bit register corresponding to both the top and bottom
entries of the transmit and receive FIFOs, respectively. Data is placed by the UDC’s receive logic
into the top of the receive FIFO. The data is transferred down the FIFO to the lowest location that
is empty. When UDCDR is read, the bottom entry of the 8-bit receive FIFO is accessed. After the
read, the bottom FIFO entry is invalidated, which causes all data in the FIFO to automatically
transfer down one location.
When UDCDR is written, the topmost FIFO entry of the 8-bit transmit FIFO is accessed. After a
write, the data is automatically transferred down the FIFO to the lowest location that is empty. The
UDC’s transmit logic takes 8-bit values from the bottom of the transmit FIFO one at a time, places
the data into a serial shifter, and transmits the value out onto the UDC pins. Each time a value is
taken from the bottom entry, the location is invalidated, which causes all data in the FIFO to
automatically transfer down one location.
SA-1110 Developer’s Manual
11-75