SA1110 Datasheet, PDF (151/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
Figure 10-8. SDRAM 1-Beat Read/Write/Read Timing for 4 Bank x 4 M x 4 Bit Organization
(64 Mbit)
1
CPU Clock
Memory
Clock
23
Trcd
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
TDL+TRP+2
TDL
TRP+1 Trcd
TRP+TWR+1
SDCLK
SDCKE
command
ACT
nRAS/nSDCS
READAP
ACT WRITEAP
ACT READAP
nSDRAS
nSDCAS
DRA13-12
Bank
DRA11
Row
DRA10 _Row
DRA9-0 Row Col
nWE
RD/nWR
Bank
Row
Row
Row Col
Bank
Row
Row
Row Col
nCAS/DQM
D
D0
D0
D0
Contents of DRAM register fields:
last
time
first
MDCNFG:DTIM0=1 MDCNFG:DWID0=0 MDCAS00=0101 0101 0101 0101 0101 0101 0101 0111(binary)
MDCNFG:DRAC0=5 MDCNFG:CDB20=0 MDCNFG:TRP0=1 MDCNGF:TDL0=2 MDCNFG:TWR0=3
A6636-02
SA-1110 Developer’s Manual
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