SA1110 Datasheet, PDF (53/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Coprocessors
Instruction Breakpoint Address
and Control Register (IBCR)
Write-Only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction Address Breakpoint Value
E
Bits
0
1
31..2
Name
E
—
Address break enable/disable.
0 – Disable
1 – Enable
Reserved.
Should be written as zero.
Address breakpoint address.
Description
5.2.14
Register 15 – Test, Clock, and Idle Control
Register 15 is a write-only register. The CRm and OPC_2 fields are used to encode the following
control operations. Operation for all other values of OPC_2 and CRm is unpredictable.
Function
Enable odd-word loading of the linear feedback shift
register ( LFSR)
Enable even-word loading of LFSR
Clear LFSR
Move LFSR to R14.abort
Enable clock switching
Disable clock switching
RESERVED
Wait for interrupt
OPC_2
0b001
0b001
0b001
0b001
0b010
0b010
0b010
0b010
CRm
0b0001
0b0010
0b0100
0b1000
0b0001
0b0010
0b0100
0b1000
SA-1110 Developer’s Manual
5-9