SA1110 Datasheet, PDF (253/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.8.9.3
11.8.9.4
11.8.9.5
11.8.9.6
Transmit Packet Error (TPE)
The transmit packet error bit acts as a status bit and will be valid while TPC is set. The TPE bit
being set will indicate that the host did not issue an ACK handshake to the current packet. The TPE
bit will be cleared when the TPC bit is cleared.
Transmit Underrun (TUR)
The transmit underrun bit will be set if the transmit FIFO experiences an underrun. This bit will be
valid when the TPC bit is set. When the UDC experiences an underrun, the packet is shortened and
the CRC is corrupted to ensure that the host discards the packet. The TUR bit will be cleared when
the TPC bit is cleared.
Sent STALL (SST)
The sent stall bit indicates that a STALL handshake was issued to the host. The CPU writes a one to
this bit to clear it. When this bit is cleared the transmit FIFO is flushed.
Force STALL (FST)
The CPU can set the force stall bit to force the UDC to issue a STALL handshake to all IN tokens.
STALL handshakes will continue to be sent until the CPU clears this bit. The sent stall bit (4) will
be set when the STALL state is actually entered (this may be delayed if the UDC is active when the
FST bit is set), and the STALL state will not be exited until both the FST and SST bits are cleared.
When the host sends a command, such as ClearFeature(HALT), the UDC is required to reinitialize
its data toggle flag back to DATA0. In order to reinitialize this internal flag, software must:
1. Set the FST bit and wait for it to set.
2. Clear the FST bit and wait for it to clear.
3. Clear the SST bit and wait for it to clear.
SA-1110 Developer’s Manual
11-73