SA1110 Datasheet, PDF (156/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
If any of the DRAM require a full burst (all rows) CBR upon exiting self-refresh, the programmer
may use repeated single (nonburst) accesses to any disabled DRAM bank.
10.5 Static Memory Interface
The static memory interface is comprised of six chip selects, nCS 5:0. nCS 2:0 are each
configurable for nonburst ROM or Flash memory, burst ROM or Flash, or SRAM. nCS 5:3 are
each configurable for nonburst ROM or Flash, burst ROM or Flash, or SRAM-like variable latency
I/O devices. The variable latency I/O interface differs from SRAM in that it allows the use of data
ready input signal, RDY, to insert a variable number of memory cycle wait states.The data bus
width for each chip select region may be programmed to be 16-bit or 32-bit. nCS 3:0 are also
configurable for SMROM, but only for 32-bit data busses. nOE is asserted for all reads. nWE is
asserted for Flash and SRAM writes. For SRAM and variable latency I/O implementations,
nCAS/DQM 3:0signals are used for the byte enables, where nCAS/DQM 3 corresponds to the
MSB. The SA-1110 supplies 26 bits of byte address (A 25:0) for access of up to 64 Mbytes per chip
select. A 0 is not used in 16-bit wide bus systems and A 1:0 are not used in 32-bit wide systems.
The RT fields in the MSCx registers specify the type of memory: nonburst ROM or Flash; nonburst
ROM, SRAM, or variable latency I/O; burst-of-four ROM or Flash; or burst-of-eight ROM or
Flash. The RBW fields specify the bus width for the memory space selected by nCS 5:0. If a 16-bit
bus width is specified, transactions take place across data pins D 15:0. The SMROM_EN pin
and/or SMCNFG register must be used to configure nCS 3:0 for SMROM.
Table 10-9 provides a comparison of supported static memory types.
Table 10-9. Summary of Static Memory and Variable Latency I/O Capabilities
MSCx:
RT
Device
Type
Chip
Selects
Nonburst
00
ROM or
nCS 5:0
Flash
Nonburst
01
ROM or
nCS 2:0
SRAM
01
Variable
Latency I/O
nCS 5:3
Burst-of-4
ROM or
10
Flash
nCS 5:0
(nonburst
writes)
Burst-of-8
ROM or
11
Flash
nCS 5:0
(nonburst
writes)
Directions
Supported
for Single
Internal
Transfers
Directions
Supported
for Burst
Internal
Transfers
Burst
Read
Address
Assert
Timing (Memory Clocks)
nOE
Assert
Burst
nOE
De-
assert
Burst
Write
Address
Assert
nWE
Assert
Burst
nWE
De-
assert
Reads,
Writes
Reads
RDF+1 RDF+1 0
N/A
RDN+1 N/A
Reads,
Writes
Reads,
Writes
Reads,
Writes
Reads,
Writes
Reads,
Writes
Reads
RDF+1 RDF+1 0
RDN+2 RDN+1 1
RDF+
RDN+2+
waits
RDF+1+
waits
RDN+1
RDF+
RDN+2+
waits
RDF+1+
waits
RDN+1
RDF+1 RDF+1
(0,4)
RDN+1
(0,4)
RDN+1
0
(1:3, 5:7) (1:3, 5:7)
N/A
RDF+1 N/A
Reads,
Writes
Reads
RDF+1 RDF+1
(0)
RDN+1
(0)
RDN+1
0
(1:7)
(1:7)
N/A
RDF+1 N/A
10-42
SA-1110 Developer’s Manual