SA1110 Datasheet, PDF (147/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
Figure 10-6 shows the rate of the shift registers during FPM or EDO DRAM nCAS timing for
burst-of-eight transactions.
Figure 10-6. Dram Burst-of-Eight Transactions
Memory Clock
nRAS
TRP+1
nCAS
ADDR Row COL COL+4 COL+8 COL+12 COL+16 COL+20 COL+24 COL+28
Reads:
nOE
Read RD/nWR
Read Data
Writes:
nWE
Write RD/nWR
D0
D1
D2
D3
D4
D5
D6
D7
Write Data
D0
D1
D2
D3
D4
D5
D6
D7
Contents of DRAM register fields:
last
time
first
MDCAS01 = 11 0001 1000 1100 (binary) MDCAS00 = 0110 0011 0001 1000 1100 0110 0000 0111 (binary)
MDCNFG: TRP0 = 4 MDCNFG: CDB20 = 1 TDL0 = 00
A6634-02
10.4.3
SDRAM Overview
The SA-1110 supports most x4, x8, x16, and x32 SDRAM. There are fifteen multiplexed
row/column address signals (DRA14-0), four command select signals (nRAS/nSDCS 3:0), four data
qualifiers for byte selection (nCAS/DQM 3:0), thirty-two data signals (D 31:0), a write enable signal
(nWE), a row address strobe (nSDRAS), a column address strobe (nSDCAS), two memory clocks
(SDCLK 2:1), and a memory clock enable (SDCKE 1).
Whenever an SDRAM bank is enabled, a mode register set (MRS) command is sent to the SDRAM
devices. MRS commands always configure SDRAM internal mode registers for sequential (or
linear) burst type and a burst length of one, while the CAS latency is determined by the TDL0 or
SA-1110 Developer’s Manual
10-33