SA1110 Datasheet, PDF (267/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
Figure 11-26. 4PPM Modulation Example
Original
Byte Order
Nibble 3
1
0
Nibble 2
1
1
Nibble 1
0
0
Nibble 0
0
1
Reordered
Nibbles
0
1
Nibble 0
0
0
Nibble 1
1
1
Nibble 2
1
0
Nibble 3
Chips
Timeslots
4PPM
Data
1
2
3
4
1234123412341234
125ns
Receive data sample counter frequency = 6X pulse width; each timeslot sampled on third clock.
11.10.2.2 HSSP Frame Format
When the 4-Mbps transmission rate is used, the high-speed serial/parallel (HSSP) interface within
the ICP is used along with the 4PPM bit encoding. The HSSP frame format is shown in
Figure 11-27.
Figure 11-27. High-Speed Serial Frame Format for IrDA Transmission (4.0 Mbps)
64 chips
8 chips
Preamble
Start Flag
Start Flag
Preamble
4 chips
(8 bits)
4 chips
(8 bits)
8180 chips
max
(2045 bytes)
16 chips
(32 bits)
Address
Control
(optional)
Data
CRC-32
|0000|1100|0000|1100|0110|0000|0110|0000|
|0000|1100|0000|1100|0000|0110|0000|0110|
|1000|0000|1010|1000|... repeated 16 times
8 chips
Stop Flag
Stop Flag
The preamble, start, and stop flags are a mixture of chips that contain either 0, 1, or 2 pulses within
the four time slots. Chips with 0 and 2 pulses are used to construct flags because they represent
invalid data bit pairings (one pulse required per chip to represent one of four bit pairs). The preamble
contains 16 repeated transmissions of the four chips: 1000 0000 1010 1000; the start flag contains one
transmission of eight chips: 0000 1100 0000 1100 0110 0000 0110 0000; and the stop flag contains
one transmission of eight chips: 0000 1100 0000 1100 0000 0110 0000 0110. The address, control,
data, and CRC-32 use the standard 4PPM chip encoding to represent 2 bits per chip.
SA-1110 Developer’s Manual
11-87