SA1110 Datasheet, PDF (252/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.8.9 UDC Endpoint 2 Control/Status Register
The UDC endpoint 2 control status register contains 6 bits that are used to operate endpoint 2
(IN endpoint). The following table describes the UDC Endpoint 2 Control Status Register.
Note: Bits 7and 6 are reserved for future use.
0h 8000 0018
7
6
5
Reserved
FST
Reset
0
0
0
UDCCS2
4
SST
0
3
TUR
0
Read/Write
2
1
0
TPE
TPC
TFS
0
0
0
Bits
Name
Description
Transmit FIFO service (read-only).
0
TFS
0 – Transmit FIFO has more than 8 bytes.
1 – Transmit FIFO has 8 bytes or less.
Transmit packet complete (read/write 1 to clear).
1
TPC
0 – Error/status bits invalid.
1 – Transmit packet has been sent and error/status bits are valid.
Transmit packet error (read-only).
2
TPE
0 – Transmit packet was received with no errors.
1 – Transmit packet has errors and the host did not issue ACK. Valid only when RPC is set.
Transmit FIFO underrun.
3
TUR
1 – Transmit FIFO experienced an underrun. Valid only when TPC is set.
Sent STALL (read/write 1 to clear).
4
SST
1 – STALL handshake was sent. Valid only when TPC is set.
Force STALL (read/write).
5
FST
1 – Issue STALL handshakes to IN tokens.
Reserved.
7..6
—
Always read zero.
The following subsections provide detailed information on the UDC Endpoint 2 Control Status
Register.
11.8.9.1
Transmit FIFO Service (TFS)
The transmit FIFO service bit will be active if there are 8 or less (out of 16) bytes remaining in the
transmit FIFO. This bit will be used as a DMA request to trigger the DMA unit to service the
transmit FIFO.
11.8.9.2
Transmit Packet Complete (TPC)
The transmit packet complete bit will be set by the UDC when an entire packet has been sent to the
host. When this bit is set, the TIR bit in the UDC status/interrupt register will be set if transmit
interrupts are enabled. This bit can be used to validate the other status/error bits in the endpoint 2
control/status register. The TPC bit gets cleared by writing a one to it. The UDC will issue NAK
handshakes to all IN tokens while this bit is set.
11-72
SA-1110 Developer’s Manual