SA1110 Datasheet, PDF (262/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.9.4 GPCLK Control Registers 2 and 3
GPCLK Control Register 2 (GPCLKR2) contains the upper 4 bits and GPCLK Control Register 3
(GPCLKR3) the lower 8 bits of the baud rate divisor field.
Note: A question mark (?) signifies that the Reset value of that bit is undefined when the processor has
completed its reset cycle.
11.9.4.1
Baud Rate Divisor (BRD)
The 12-bit baud rate divisor (BRD) field is used to select the baud or bit rate of the GPCLK output
clock. A total of 4096 different baud rates can be selected, ranging from a minimum of
900 Hz to 3.6864 MHz. The baud rate generator uses the 3.6864-MHz clock generated by the
on-chip PLL and first divides it by the programmable baud rate using BRD. The resultant clock is
sent out GPIO pin 16. The resultant baud rate given a specific BRD value, or required BRD value
given a desired baud rate, can be calculated using the following two respective equations, where
BRD is the decimal equivalent of the unsigned binary value programmed within the bit field:
BaudRate = -3-₍--.-_B-6---8_R---6--_D--4---^×-+---¹--1-⁰--₎-6-
BRD
=
3----.-6----8---6----4---×_----1_---0_---6-
BaudRate
–
1
The following tables show the bit locations corresponding to the baud rate divisor field that is split
between two registers. The upper 4 bits of BRD reside within GPCLKR1and the lower 8 bits reside
within GPCLKR2. The GPCLK must be disabled (SUS=0) whenever these registers are written.
Note that writes to reserved bits are ignored and reads return zeros; question marks indicate that the
values are unknown at reset.
Reset
0h 8002 006C
7
6
5
Reserved
0
0
0
GPCLKR2
4
3
0
?
Read/Write
2
1
0
BRD 11..8
?
?
?
Bits
Name
Description
Baud rate divisor.
3..0
BRD 11..8 Encoded value (from 0 to 4095). Used to generate the baud rate of the GPCLK.
Baud Rate = 3.6864x10⁶/((BRD+1)), where BRD is a decimal value.
7..4
—
Reserved.
11-82
SA-1110 Developer’s Manual