SA1110 Datasheet, PDF (366/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

AC Parameters
13.6 Timing Parameters
Table 13-3 lists AC timings for SDRAM and SMROM. It includes frequency-dependent guidelines
for using the delayed latching option on read data. This option is controlled by the contents of the
CAS Waveform Rotate Registers (MDCASnn), as described in Section 10.2.3.2, “MDCAS
Registers with SDRAM and SMROM” on page 10-19.
Table 13-4 lists the AC timing guidelines for asynchronous memory types. Each parameter
references the SA-1110’s internal memory clock. These parameters are not guaranteed for use
under all operating conditions.
Table 13-5 lists the AC timing parameters for the SA-1110 MCP interface and LCD controller. For
timing parameters for 1.55-V devices, contact the Intel Massachusetts Customer Technology
Center.
Table 13-3. SA-1110 AC Timing Specifications and Guidelines for SDRAM/SMROM
Pin Name
AB or BB
Symbol
Parameter
(133MHz
or 206MHz
maximum
operating
SDCLK
Frequency
(MHz)
Non-Delayed
or Delayed
Latching on
Read Data
Min
Unit Note
frequency)
Memory Bus
A<25:0>, D<31:0>,
nRAS/nSDCS<3:0>
, nCAS/DQM<3:0>,
nCS<3:0>,
nSDRAS, nSD-
Tsdos
SDRAM/
SMROM
output setup
time to
SDCLK<2:0>
AB
CAS, nWE, nOE,
rise
BB
SDCKE<1:0>
A<25:0>, D<31:0>,
nRAS/nSDCS<3:0>
, nCAS/DQM<3:0>,
nCS<3:0>,
nSDRAS, nSD-
Tsdoh
SDRAM/
SMROM
output hold
time from
SDCLK<2:0>
AB
CAS, nWE, nOE,
rise
BB
SDCKE<1:0>
D<31:0>
SDRAM/
SMROM
AB
Tsdis
data input
setup time to
SDCLK<2:0>
BB
rise
D<31:0>
AB
SDRAM/
SMROM
data input
Tsdih
hold time
from
SDCLK<2:0>
rise
BB
28 - 66
4.2 ns
28 - 103
4.2 ns
28 - 66
2.2 ns
28 - 103
28 - 55
55 - 66
28 - 62
62 - 103
28 - 55
55 - 62
62 - 66
28 - 62
62 - 69
69 - 77
77 - 84
84 - 103
2.2 ns
Non-Delayed 11.5 ns
1
Delayed
3.4 ns
1
Non-Delayed 9.3 ns
1
Delayed
2.7 ns
1
Non-Delayed 2.7 ns
1
Delayed
4.8 ns 1, 2
Delayed
3.9 ns 1, 2
Non-Delayed 2.7 ns
1
Delayed
4.6 ns 1, 2
Delayed
3.8 ns 1, 2
Delayed
3.2 ns 1, 2
Delayed
2.7 ns
1
Notes:
1. Tsdis and Tsdih are specified only for delayed read data latching at the maximum SDCLK frequency or
non-delayed read data latching at one-half the maximum SDCLK frequency. All other Tsdis and Tsdih values
should be considered as guidelines, and are not guaranteed for use under all operating conditions.
2. The larger Tsdih values can be achieved by intentionally adding delay to SDCLK (e.g.- by using serpentine
board routing). However, the system designer must carefully evaluate the resulting degradation to input setup
13-4
SA-1110 Developer’s Manual