SA1110 Datasheet, PDF (182/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
Figure 11-1. Peripheral Control Module Block Diagram
ARM^®* System Bus
DMA
Controller
ARM Peripheral Bus
LCD
Controller
Serial Port 0 Serial Port 1 Serial Port 2 Serial Port 3 Serial Port 4
UDC
GPCLK/UART
ICP
UART
MCP/SSP
L_PCLK L_BIAS UDC+ UDC- TXD1 RXD1 TXD2 RXD2 TXD3 RXD3 TXD4 SCLK
* ARM is a registered trademark of ARM Limited.
A6833-01
Table 11-1.
Peripheral Control Modules’ Register Width and DMA Port Size
Peripheral
LCD controller
Serial port 0: UDC
Serial port 1: UART
Serial port 2: ICP
UART
HSSP
Serial port 3: UART
Serial port 4:
MCP
SSP
Peripheral pin controller (PPC)
Register Width /
DMA Port Size
32
8
8
8
8
8
16
16
32
DMA Burst Size
4 words
8 bytes
4 bytes
4 bytes
8 bytes
4 bytes
8 bytes
8 bytes
N/A
11.2
Memory Organization
Several of the serial ports contain more than one serial engine. Each individual engine is
self-contained (no shared logic or registers) and implements a separate serial protocol. Serial ports
1, 2, and 4 each contain two separate serial engines, totalling eight separate serial engines within all
five serial ports. Each of the eight serial engines, including the peripheral pin controller (PPC), has
been allocated a separate 64 Kbyte block on-chip memory space in which its registers reside.
Although the register width of individual units varies, each register is right justified on word
boundaries. All register accesses via the CPU must be performed using word reads and writes. This
chapter includes a summary of individual peripheral registers. See Appendix A, “Register
Summary,” for a complete summary of all on-chip registers.
11-2
SA-1110 Developer’s Manual