SA1110 Datasheet, PDF (146/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
Figure 10-5 shows the rate of the shift registers during DRAM nCAS timing for a single-beat
transaction.
Figure 10-5. DRAM Single-Beat Transactions
CPU Clock
Memory Clock
nRAS
TRP+1
nCAS
ADDR
Reads:
nOE
ROW
COL
ROW
Read RD/nWR
Read Data
D0
Writes:
nWE
Write RD/nWR
Write Data
DO
Contents of DRAM register fields:
time
last
first
MDCAS01 = 11 0001 1000 1100 (binary) MDCAS00 = 0110 0011 0001 1000 1100 0110 0000 0111 (binary)
MDCNFG:TRP0 = 4 MDCNFG:CDB20 = 1 TDL0 = 00
A6633-02
10-32
SA-1110 Developer’s Manual