SA1110 Datasheet, PDF (298/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
Reset
0h 8005 000C
7
6
Reserved
0
0
Bits
Name
2
BRK
3
RIE
4
TIE
5
LBM
7..6
—
UTCR3
Read/Write
5
4
3
2
1
0
LBM
TIE
RIE
BRK
TXE
RXE
?
?
?
?
0
0
(Sheet 2 of 2)
Description
Break.
0 – UART in normal operation.
1 – Force TXD3 low (all bits in the frame are a zero) to generate a break.
Receive FIFO interrupt enable.
0 – Receive FIFO one- to two-thirds full (or more) and receiver idle conditions do not
generate an interrupt (RFS and RID bit ignored).
1 – Receive FIFO one- to two-thirds full (or more) and receiver idle conditions generate an
interrupt (state of RFS and RID sent to interrupt controller).
Transmit FIFO interrupt enable.
0 –Transmit FIFO half-full or less condition does not generate an interrupt (TFS bit
ignored).
1 – Transmit FIFO half-full or less condition generates an interrupt (state of TFS sent to
interrupt controller).
Loopback mode.
0 – Normal serial port operation enabled.
1 – Output of transmit serial shifter is connected to input of receive serial shifter internally
and control of TXD3 and RXD3 pins is given to the PPC unit.
Reserved.
11.11.6
UART Data Register
The UART data register (UTDR) is an 8-bit register corresponding to both the top and bottom
entries of the transmit and receive FIFOs, respectively.
When UTDR is read, the lower 8 bits of the bottom entry of the 10-bit receive FIFO are accessed. As
data enters the top of the receive FIFO, bits 8..10 are used to indicate various error conditions that
occur during reception of each piece of data. The error bits are transferred down the FIFO along with
the value that caused the error. When data reaches the bottom, bit 8 of the bottom FIFO entry is
automatically transferred to the parity error (PRE) flag, bit 9 to the framing error (FRE) flag, and bit
10 to the receiver overrun (ROR) flag, all within the UART status register. The user can read these
flags to determine if the value at the bottom of the FIFO encountered an error during reception. After
checking the flags, the FIFO value can then be read, which causes the data in the next location of the
receive FIFO to automatically be transferred down to the bottom entry and its error bits to be
transferred to the status register. The error in FIFO (EIF) flag bit is set whenever one or more of the
error bits (8..10) is set within any of the bottom four entries of the receive FIFO and is cleared when
no error bits are set in the bottom four entries of the FIFO. When EIF is set, an interrupt is generated
and receive FIFO DMA requests are disabled so that the user can manually empty the FIFO, always
checking the parity, framing, and overrun flags in the status register first before removing the data
values from the FIFO. After each entry is removed, the user should check the EIF bit to see if any
errors remain, and repeat the procedure until all errors are flushed from the FIFO. Once EIF is
cleared, servicing of the receive FIFO by the DMA controller is automatically reenabled.
11-118
SA-1110 Developer’s Manual