SA1110 Datasheet, PDF (155/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
Figure 10-11. DRAM/SDRAM CBR Refresh Cycle
CPU Clock
Memory
Clock
SDCLK
SDCKE
command
nCAS/DQM
nRAS/nSDCS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PALL
SDRAM only
CBR
TRASR+1
ACT
nSDRAS
nSDCAS
DRA13-12
Bank
DRA11
Row
DRA10
Row
DRA9-0
Row
nWE
A6638-01
10.4.7
DRAM/SDRAM Self-Refresh in Sleep Mode
The SA-1110 puts the DRAM into the self-refresh state prior to entering sleep mode by driving all
nCAS/DQM low, then driving all nRAS/nSDCS low (just as for a normal CBR refresh cycle), and
maintaining them low while core power (VDD) and clocks are turned off. The SDRAM
self-refresh command (SLFRSH) differs from auto-refresh command (CBR) in that SLFRSH
drives the SDCKE 1:0 signals low. They will continue to be held low throughout sleep.
SDCLK 2:0 stop running throughout sleep: SDCLK 2:1 are held high; SDCLK 0 is held low if
auto-power-down is enabled, or held high if auto-power-down is disabled.
See Section 9.5 for details on how to bring DRAM out of self-refresh mode. See Section 10.4.5 and
section 10.7.1 on page 64 for details on how to bring SDRAM out of self-refresh mode. An access
to a DRAM bank while the DRAM interface is in self-refresh mode has undefined results, but the
DRAM remains in self-refresh.
SA-1110 Developer’s Manual
10-41