SA1110 Datasheet, PDF (260/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.9.2.3 Sample Clock Direction (SCD)
When the sample clock function is enabled (SCE=1), the sample clock direction (SCD) bit is used
to select whether the sample clock is an input from or an output to GPIO pin 16. When SCD=0, the
sample clock is input using GPIO pin 16 and is not used. When SCD=1, the sample clock, which is
generated within the GPCLK unit (the clock that is output after dividing the 3.6864-MHz reference
by the programmable BRD field), is output to GPIO pin 16 in frequency ranging from 900 Hz to
3.6864 MHz.
The following table shows the location of all bit fields located in GPCLK control register 0
(GPCLKR0). The GPCLK must be disabled (SUS=0) when changing the state of any bit within
this register.
Note: A question mark (?) signifies that the Reset value of that bit is undefined when the processor has
completed its reset cycle.
Address: 0h 8002 0060
Bit
Reset
7
Reserved
?
6
Reserved
?
5
SCD
?
GPCLKR0
4
SCE
?
3
Reserved
?
Read/Write
2
Reserved
?
1
Reserved
?
0
SUS
0
Bit Name
Description
0
SUS
GPCLK/UART select.
0 – GPCLK mode selected.
1 – UART mode selected.
Note: For SUS=0, TXD1 and RXD1 control is given to the PPC unit. If UPR is set in
the PPC unit, SUS is ignored, the UART uses GPIO<14> to transmit and GPIO<15>
to receive data, and serial port 1 defaults to GPLCK mode. The user must also
program the GAFR and GPDR registers appropriately in the GPIO unit.
1
Reserved Reserved for Future Expansion.
2
Reserved Reserved for Future Expansion.
3
Reserved Reserved for Future Expansion.
4
SCE
Sample clock enable.
0 – Sample clock disabled.
1 – Sample clock enabled.
5
SCD
Sample clock direction.
0 – If sample clock enabled, it is input on GPIO pin 16 and is not used.
1 – The sample clock which is generated within the GPCLK unit (the clock that is output
after dividing the 3.6864 MHz reference by the programmable BRD field), is output to the
GPIO pin 16 in the frequency range of 900 Hz – 3.6864MHz..
6
Reserved Reserved for Future Expansion.
7
Reserved Reserved for Future Expansion.
11-80
SA-1110 Developer’s Manual