SA1110 Datasheet, PDF (7/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

10.5.1 ROM Interface Overview ........................................................................... 10–43
10.5.2 ROM Timing Diagrams and Parameters.................................................... 10–43
10.5.3 SRAM Interface Overview ......................................................................... 10–46
10.5.4 SRAM Timing Diagrams and Parameters.................................................. 10–46
10.5.5 Variable Latency I/O Interface Overview ................................................... 10–48
10.5.6 Variable Latency I/O Timing Diagrams and Parameters ........................... 10–48
10.5.7 FLASH Memory Interface Overview .......................................................... 10–51
10.5.8 FLASH Memory Timing Diagrams and Parameters ................................. 10–51
10.5.9 SMROM Overview ..................................................................................... 10–52
10.5.10 SMROM Commands.................................................................................. 10–52
10.5.11 SMROM State Machine ............................................................................. 10–53
10.6 PCMCIA Overview ........................................................................................ 10–55
10.6.1 32-Bit Data Bus Operation........................................................................ 10–57
10.6.2 External Logic for PCMCIA Implementation ............................................10–58
10.6.3 PCMCIA Interface Timing Diagrams and Parameters ...............................10–61
10.7 Memory Interface Reset and Initialization ..................................................... 10–63
10.7.1 Hardware or Sleep Reset Procedures ....................................................... 10–64
10.7.2 Software or Watchdog Reset Procedures ................................................. 10–65
10.8 Alternate Memory Bus Master Mode............................................................. 10–65
11
Peripheral Control Module ........................................................................................ 11–1
11.1 Read/Write Interface ....................................................................................... 11–1
11.2 Memory Organization ...................................................................................... 11–2
11.3 Interrupts ......................................................................................................... 11–3
11.4 Peripheral Pins ................................................................................................ 11–4
11.5 Use of the GPIO Pins for Alternate Functions................................................. 11–5
11.6 DMA Controller................................................................................................ 11–6
11.6.1 DMA Register Definitions............................................................................. 11–6
11.6.1.1 DMA Device Address Register (DDARn) ..............................................11–7
11.6.1.2 DMA Control/Status Register (DCSRn) ............................................... 11–10
11.6.1.3 DMA Buffer A Start Address Register (DBSAn) .................................. 11–11
11.6.1.4 DMA Buffer A Transfer Count Register (DBTAn) ................................ 11–12
11.6.1.5 DMA Buffer B Start Address Register (DBSBn) .................................. 11–12
11.6.1.6 DMA Buffer B Transfer Count Register (DBTBn) ................................ 11–12
11.6.2 DMA Operation .........................................................................................11–13
11.6.3 DMA Register List...................................................................................... 11–13
11.7 LCD Controller............................................................................................... 11–15
11.7.1 LCD Controller Operation .......................................................................... 11–17
11.7.1.1 DMA to Memory Interface.................................................................... 11–17
11.7.1.2 Frame Buffer........................................................................................ 11–17
11.7.1.3 Input FIFO ........................................................................................... 11–22
11.7.1.4 Lookup Palette..................................................................................... 11–22
11.7.1.5 Color/Gray-Scale Dithering.................................................................. 11–23
11.7.1.6 Output FIFO.........................................................................................11–23
11.7.1.7 LCD Controller Pins ............................................................................. 11–24
11.7.2 LCD Controller Register Definitions........................................................... 11–24
11.7.3 LCD Controller Control Register 0 ............................................................. 11–25
11.7.3.1 LCD Enable (LEN) ............................................................................... 11–25
11.7.3.2 Color/Monochrome Select (CMS)........................................................ 11–25
11.7.3.3 Single-/Dual-Panel Select (SDS) .........................................................11–25
11.7.3.4 LCD Disable Done Interrupt Mask (LDM) ............................................11–28
SA-1110 Developer’s Manual
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