SA1110 Datasheet, PDF (186/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.6 DMA Controller
The DMA controller consists of six independent DMA channels. Each channel can be configured
to service any of the serial controllers. Two channels are required to service a full-duplex serial
controller. The DMA controller is intended to relieve the processor of the interrupt overhead in
servicing these ports with programmed I/O. If desired, any or all peripherals (except the UDC) may
be serviced with programmed I/O instead of DMA. Each peripheral is capable of requesting
processor service through its own interrupt lines or through a DMA request.
The DMA controller consists of a set of configuration and control registers for each channel and a
common data transfer engine that services the active channel. Channels are serviced in a fixed
priority sequence if the DMA receives multiple requests. Each channel is serviced in increments of
that device’s burst size and delivered in the granularity of that device’s port width (byte or
half-word). The burst size and port width for each device is programmed in the channel registers
and is based on the device’s FIFO depth and bandwidth needs. When multiple channels are actively
executing, each channel is serviced with a burst of data after which the DMA controller may
perform a context switch to another active channel. The DMA controller performs context switches
based on whether a channel is active, whether its target device is currently requesting service (the
FIFO is half-empty), and where that channel lies in the priority scheme.
Data transfers are performed between a device (one of the serial controllers) and memory (ROM,
RAM, Flash, SRAM, or DRAM). DMA transfers to and from PCMCIA space are not permitted.
During a write, a burst of data is read from memory as words into a buffer inside the DMA
controller. That data is then written to the device according to the device’s port width and the state
of the endian bit (E). During a read, data is read from the device according to the device’s port
width and then sent to memory as words. The organization of the bytes inside that word is
determined again by the endian bit (E).
The control registers for each channel include two starting address registers and two transfer count
registers. These registers should be programmed by the system at the start of the transfer. The
registers control two rotating buffers for use during a transfer. These buffers, designated buffer A
and buffer B, can be chained together so that when a transfer to (or from) one buffer completes, the
transfer to (or from) the other begins immediately. By interrogating the status information in the
channel control/status register, the user can safely update the address pointer and transfer count of
the inactive buffer.
11.6.1 DMA Register Definitions
Each DMA channel is supported by six 32-bit registers as part of the DMA controller hardware.
These registers are the DMA device address register (DDARn), DMA control/status register
(DCSRn), DMA buffer A start address (DBSAn), DMA buffer B start address (DBSBn), DMA
buffer A transfer count (DBTAn), and DMA buffer B transfer count (DBTBn). (The n is a value
from 0 to 5 and is the channel number.) A register summary including physical addresses is
provided at the end of this section.
Note: A question mark (?) signifies that the Reset value of that bit is undefined when the processor has
completed its reset cycle.
11-6
SA-1110 Developer’s Manual