SA1110 Datasheet, PDF (6/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

9.5.3.6 Booting After Sleep Mode...................................................................... 9–30
9.5.3.7 Reviving the DRAMs from Self-Refresh Mode ...................................... 9–31
9.5.4 Notes on Power Supply Sequencing ........................................................... 9–31
9.5.5 Assumed Behavior of an Intel® StrongARM SA-1110
System in Sleep Mode................................................................................. 9–31
9.5.6 Pin Operation in Sleep Mode....................................................................... 9–33
9.5.7 Power Manager Registers ........................................................................... 9–34
9.5.7.1 Power Manager Control Register (PMCR) ............................................ 9–34
9.5.7.2 Power Manager General Configuration Register (PCFR) ..................... 9–35
9.5.7.3 Power Manager PLL Configuration Register (PPCR)............................ 9–37
9.5.7.4 Power Manager Wake-Up Enable Register (PWER) ............................ 9–37
9.5.7.5 Power Manager Sleep Status Register (PSSR) .................................... 9–38
9.5.7.6 Power Manager Scratch Pad Register (PSPR) ..................................... 9–40
9.5.7.7 Power Manager GPIO Sleep State Register (PGSR)............................ 9–40
9.5.7.8 Power Manager Oscillator Status Register (POSR) .............................. 9–41
9.5.8 Power Manager Register Locations ............................................................ 9–41
9.6 Reset Controller .............................................................................................. 9–42
9.6.1 Reset Controller Registers .......................................................................... 9–42
9.6.1.1 Reset Controller Software Reset Register (RSRR) ............................... 9–42
9.6.1.2 Reset Controller Status Register (RCSR) ............................................. 9–44
9.6.2 Reset Controller Register Locations ............................................................ 9–44
10
Memory and PCMCIA Control Module ..................................................................... 10–1
10.1 Overview of Operation .................................................................................... 10–2
10.1.1 Memory System Examples .......................................................................... 10–4
10.1.2 Types of Memory Accesses ........................................................................ 10–7
10.1.3 Reads .......................................................................................................... 10–7
10.1.4 Writes ......................................................................................................... 10–7
10.1.5 Transaction Summary ................................................................................ 10–7
10.1.6 Read-Lock-Write.......................................................................................... 10–8
10.1.7 Aborts and Nonexistent Memory ................................................................ 10–8
10.2 Memory Configuration Registers.................................................................... 10–9
10.2.1 DRAM Configuration Register (MDCNFG) ................................................ 10–10
10.2.2 DRAM Refresh Control Register (MDREFR)............................................. 10–14
10.2.3 CAS Waveform Rotate Registers (MDCAS00, MDCAS01, MDCAS02,
MDCAS20, MDCAS21, MDCAS22) .......................................................... 10–18
10.2.3.1 MDCAS Registers with Asynchronous DRAM..................................... 10–18
10.2.3.2 MDCAS Registers with SDRAM and SMROM .................................... 10–19
10.2.4 Static Memory Control Registers (MSC2 – 0) ........................................... 10–20
10.2.5 Expansion Memory (PCMCIA) Configuration Register (MECR)................ 10–23
10.3 SMROM Configuration Register (SMCNFG)................................................. 10–25
10.3.1 Changing SMROM RAS Latency .............................................................. 10–28
10.4 Dynamic Interface Operation ........................................................................ 10–29
10.4.1 DRAM Overview ........................................................................................ 10–29
10.4.2 DRAM Timing ............................................................................................ 10–31
10.4.3 SDRAM Overview...................................................................................... 10–33
10.4.4 SDRAM Commands .................................................................................. 10–34
10.4.5 SDRAM State Machine.............................................................................. 10–35
10.4.6 DRAM/SDRAM Refresh ............................................................................ 10–40
10.4.7 DRAM/SDRAM Self-Refresh in Sleep Mode ............................................. 10–41
10.5 Static Memory Interface ................................................................................ 10–42
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SA-1110 Developer’s Manual