SA1110 Datasheet, PDF (51/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Coprocessors
5.2.11
5.2.12
Function
Load Buffer 3 with eight words
Disable user-mode MCR access
Enable user-mode MCR access
OPC_2
0b010
0b100
0b101
CRm
0b1011
0b0000
0b0000
Data
Virtual address
Ignored
Ignored
See Chapter 6, “Caches, Write Buffer, and Read Buffer” for details on the use and operation of the
read buffer.
Registers 10 – 12 RESERVED
Accessing registers 10 – 12 may yield unpredictable results.
Register 13 – Process ID Virtual Address Mapping
The SA-1110 supports the remapping of virtual addresses through a process ID (PID) register. The
6-bit PID value is OR’ed with bits 30..25 of the virtual address when bits 31..25 of the virtual
address are zero. This effectively remaps the address to one of 64 “slots” in the lower 2 Gbyte
address space. The following table shows the OPC_2 and CRm field encodings used to access the
process ID register. This register is zero at reset and if left unmodified, effectively disables the
remapping function. As such, no explicit enable or disable function is necessary. Reserved bits read
as zero and must be written as zero. This register is readable and writable.
Function
Access process ID register
OPC_2
0b000
The following figure shows the format of the process ID register.
CRm
0b0000
Register 13 – Process ID
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Process ID
Reserved
5.2.13
Register 14 – Debug Support (Breakpoints)
The SA-1110 supports address and data breakpoints through register 14 of coprocessor 15. The
instruction formats follow. For a description of the breakpoint operation, see Chapter 15, “Debug
Support”. The following table shows the OPC_2 and CRm field encodings used to access the
address and data breakpoints.
SA-1110 Developer’s Manual
5-7