SA1110 Datasheet, PDF (283/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.10.10.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable
interrupt)
The transmit FIFO service request flag (TFS) is a read-only bit that is set when the transmit FIFO is
nearly empty and requires service to prevent an underrun. TFS is set any time the transmit FIFO
has eight or fewer entries of valid data (half-full or less), and is cleared when it has nine or more
entries of valid data. When the TFS bit is set, an interrupt request is made unless the transmit FIFO
interrupt request mask (TIE) bit is cleared. The state of TFS is also sent to the DMA controller, and
can be used to signal a DMA service request. Note that TIE has no effect on the generation of the
DMA service request. After the DMA or CPU fills the FIFO, such that eight or more locations are
filled within the transmit FIFO, the TFS flag (and the service request and/or interrupt) is
automatically cleared.
11.10.10.5 Receive FIFO Service Request Flag (RFS) (read-only, maskable
interrupt)
The receive FIFO service request flag (RFS) is a read-only bit that is set when the receive FIFO is
nearly filled and requires service to prevent an overrun. The amount of data that causes RFS to be
set is nondeterministic. However, the range in which RFS will be set is guaranteed. RFS is set at
some point when the receive FIFO is two- to three-fifths full (or more). The HSSP’s FIFOs are
self-timed to reduce cost and save power. As a result, the depth at which the receive FIFO service
request is generated is variable. This is the reason the receive FIFO is 20 entries deep instead of 16
like the transmit FIFO. At which entry in the FIFO the request is actually triggered is dependent on
IC process, operating temperature, and so on. The receive FIFO is designed to signal the RFS bit to
be set when it contains 12 entries of valid data. However, because of the variability of the
self-timed logic, RFS may also be set when 11, 10, or 9 entries of valid data are present within the
FIFO. Likewise, under normal circumstances, RFS is cleared when the receive FIFO has 11
remaining entries of valid data. However, again due to variations, RFS may be cleared when 10 or
9 entries of data remain.
When the RFS bit is set, a DMA service request is made. An interrupt request is also made unless
the receive FIFO interrupt request mask (RIE) bit is cleared. Even though more than eight entries
of data may exist within the receive FIFO, the user must configure the DMA burst size to eight
words. If programmed I/O is used to service the receive FIFO, a maximum of eight words may be
removed without checking if data is valid. After this point, the receive FIFO not empty (RNE) flag
must be polled before each read to see if more data remains. After the DMA or CPU empties the
FIFO such that nine or more empty locations are available within the receive FIFO, the RFS flag
(as well as the DMA and interrupt request) is automatically cleared.
SA-1110 Developer’s Manual
11-103