SA1110 Datasheet, PDF (318/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
0h 8006 0000
MCP Control Register 0: MCCR0
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
ECP
TSD
ASD
Reset 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ?
(Sheet 2 of 3)
Bits
Name
Description
Multimedia communications port enable.
0 – MCP operation disabled, control of the TXD4, RXD4, SCLK, and SFRM pins given to
the PPC to be used as general-purpose I/O pins.
16
MCE 1 – MCP operation enabled.
Note that the MCP has precedence over the SSP, if MCE=1; SSE is ignored unless the
SPR bit is set within the PPC, which allows the SSP to use GPIO pins while the MCP uses
serial port 4’s pin for transmission.
External clock select.
0 – on-chip clock used to produce the frame rate as further programmed by the CFS control
bit in MCCR1. It is also used to clock the audio and telecom sample rate counters.
17
ECS
1 – Clock input using GPIO pin 21 to select a frame rate that is an exact multiple of the
desired audio/telecom sample rate.
Frame Rate = Input Clock Frequency /(ECP x 32).
Sample Rate = Input Clock Frequency /(ECP x 32 x ASD or TSD).
A/D data sampling mode.
0 – Audio and telecom receive data is stored to their respective FIFOs whenever their receive
18
ADM
data valid bits are valid.
1– Audio and telecom receive data is stored when the receive data valid bit is set the first
time, and from that point on whenever the MCP’s audio and telecom sample rate counters
time out.
Telecom transmit FIFO interrupt enable.
0 – Telecom transmit FIFO half-full or less condition does not generate an interrupt (TTS bit
19
TTE
ignored).
1 – Telecom transmit FIFO half-full or less condition generates an interrupt (state of TTS
sent to interrupt controller).
Telecom receive FIFO interrupt enable.
0 – Telecom receive FIFO one- to two-thirds full or more condition does not generate an
20
TRE
interrupt (TRS bit ignored).
1 – Telecom receive FIFO one- to two-thirds full or more condition generates an interrupt
(state of TRS sent to interrupt controller).
Audio transmit FIFO interrupt enable.
0 – Audio transmit FIFO half-full or less condition does not generate an interrupt (ATS bit
21
ATE
ignored).
1 – Audio transmit FIFO half-full or less condition generates an interrupt (state of ATS sent
to interrupt controller).
Audio receive FIFO interrupt enable.
0 – Audio receive FIFO one- to two-thirds full or more condition does not generate an
22
ARE
interrupt (ARS bit ignored).
1 – Audio receive FIFO one- to two-thirds full or more condition generates an interrupt
(state of ARS sent to interrupt controller).
Loopback mode.
23
LBM
0 – Normal serial port operation enabled.
1 – Output of serial shifter is connected to input of serial shifter internally and control of
TXD4, RXD4, SCLK, and SFRM pins is given to the PPC unit.
11-138
SA-1110 Developer’s Manual