SA1110 Datasheet, PDF (47/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Coprocessors
5.2.2 Register 1 – Control
Register 1 is a read/write register containing control bits. All writable bits in this register are forced
low by reset. The shaded bits (also labeled r) are reserved and are not readable or writable..
Register 1 – Control
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined
XI
R S B 1 1 1WC AM
Bits
0
1
2
3
4
5
6
7
8
9
11..10
12
Name
M
A
C
W
P
D
L
B
S
R
—
I
(Sheet 1 of 2)
Description
Enable/disable
0 – On-chip memory-management unit disabled
1 – On-chip memory-management unit enabled
Address fault enable/disable
0 – Alignment fault disabled
1 – Alignment fault enabled
Data cache enable/disable
0 – Data cache disabled
1 – Data cache enabled
Write buffer enable/disable
0 – Write buffer disabled
1 – Write buffer enabled
32-bit/26-bit exception handlers.
Should always be 1.
32-bit/26-bit Data address range.
Should always be 1.
Implementation defined.
Should always be 1.
Big/little endian
0 – Little endian operation
1 – Big endian operation
System
This bit selects the access checks performed by the memory-management unit.
See the ARM Architecture Reference for more information.
ROM
This bit selects the access checks performed by the memory-management unit.
See the ARM Architecture Reference for more information.
Unused.
Undefined on Read. Writes ignored.
Instruction cache enable/disable
0 – Instruction cache disabled
1 – Instruction cache enabled
SA-1110 Developer’s Manual
5-3