SA1110 Datasheet, PDF (216/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.7.5.3
11.7.5.4
VSW does not affect generation of the frame clock signal in passive mode. Passive LCD displays
require that the frame clock is active on the rising edge of the first line clock pulse of each frame,
with adequate setup and hold time. To meet this requirement, the LCD controller’s frame clock pin
is asserted on the rising edge of the first pixel clock for each frame. The frame clock remains
asserted for the remainder of the first line as pixels are output to the display and it is then negated
on the rising edge of the first pixel clock of the second line of each frame.
End-of-Frame Line Clock Wait Count (EFW)
The 8-bit end-of-frame line clock wait count (EFW) field is used in active mode (PAS=1) to
specify the number of line clocks to insert at the end of each frame. Once a complete frame of
pixels is transmitted to the LCD display, the value in EFW is used to count the number of line clock
periods to wait. After the count has elapsed, the VSYNC (L_FCLK) signal is pulsed. EFW
generates a wait period ranging from 0 to 255 line clock cycles (setting EFW=8’h00 disables the
EOF wait count). Note that the line clock pin, L_LCLK, does not transition during the generation
of the EFW line clock periods.
In passive mode, EFW should be set to zero such that no end-of-frame waitstates are generated.
VSW should be used exclusively in passive mode to insert line clock waitstates to allow the LCD’s
DMA to fill the palette and process a number of pixels before the start of the next frame.
Beginning-of-Frame Line Clock Wait Count (BFW)
The 8-bit beginning-of-frame line clock wait count (BFW) field is used in active mode (PAS + 1) to
specify the number of line clocks to insert at the beginning of each frame. The BFW count starts
just after the VSYNC signal for the previous frame has been negated. After this has occurred, the
value in BFW is used to count the number of line clock periods to insert before starting to output
pixels in the next frame. BFW generates a wait period ranging from 0 to 255 extra line clock cycles
(BFW=8’h00 disables the BOF wait count). Note that the line clock pin, L_LCLK, does transition
during the generation of the BFW line clock wait periods.
In passive mode, BFW should be set to zero such that no beginning-of-frame waitstates are
generated. VSW should be used exclusively in passive mode to insert line clock waitstates to allow
the LCD’s DMA to fill the palette and process a number of pixels before the start of the next frame.
11-36
SA-1110 Developer’s Manual