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SA1110 Datasheet, PDF (20/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor | |||
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Introduction
Table 1-1.
Features of the SA-1110 CPU
⢠High Performance
â 150 Dhrystone 2.1 MIPS @ 133 MHz
â 235 Dhrystone 2.1 MIPS @ 206 MHz
⢠3.3 V I/O interface
⢠256-pin mini-BGA package (mBGA)
⢠32-way set-associative caches
⢠Low power (normal mode)â
â 16 Kbyte instruction cache
â <240 mW @1.55 V/133 MHz
â 8 Kbyte write-back data cache
â <400 mW @ 1.75 V/206 MHz
⢠32-entry memory-management units
⢠Integrated clock generation
â Maps 4 Kbyte, 8 Kbyte, or 1 Mbyte
â Internal phase-locked loop (PLL)
⢠Write buffer
â 3.686 MHz oscillator
â 8-entry, between 1 and 16 bytes each
â 32.768 kHz oscillator
⢠Read buffer
⢠Power-management features
â 4-entry, 1, 4, or 8 words
â Normal (full-on) mode
⢠Memory bus
â Idle (power-down) mode
â Sleep (power-down) mode
⢠Big and little endian operating modes
â Interfaces to ROM, synchronous
mask ROM (SMROM), Flash,
SRAM, SRAM-like variable latency
I/O, DRAM, and synchronous DRAM
(SDRAM)
â Supports two PCMCIA sockets
â Power dissipation, particularly in idle mode, is strongly dependent on the details of the system design.
Table 1-2.
Changes to the SA-1110 Core from the SA-110
⢠Data cache reduced from 16 Kbyte to
8 Kbyte
⢠Interrupt vector address adjust capability
⢠Hardware breakpoints
⢠Memory-management unit (MMU)
enhancements
⢠Read buffer (nonblocking)
⢠Process ID mapping
⢠Minicache for alternate data caching
1-2
SA-1110 Developerâs Manual
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