SA1110 Datasheet, PDF (203/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.7.1.5 Color/Gray-Scale Dithering
For passive displays, entries selected from the lookup palette are sent to the color/gray-scale
space/time base dither generator. Each 4-bit value is used to select one of 15 intensity levels. Note
that two of the 16 dither values are identical (always high). The color/gray intensity is controlled by
turning individual pixels on and off at varying periodic rates. For some screens, more intense
colors/grays are produced by making the average time the pixel is high longer than the average
time it is low, while other screens produce more intense colors/grays when the average time the
pixel is low is longer. The user should program the palette appropriately depending on whether a
one on the pixel line turns the pixel on or off. The dither generator also uses the intensity of
adjacent pixels in its calculations to give the screen image a smooth appearance. The proprietary
dither algorithm is optimized to provide a range of intensity values that match the eye’s visual
perception of color/gray gradations. In color mode, three separate dither blocks are used to process
the three color components: red, green, and blue. Table 11-7 summarizes the duty cycle and
resultant intensity level for all 15 color/gray-scale levels.
Table 11-7.
Color/Gray-Scale Intensities and Modulation Rates
Dither Value
(4-Bit Value from Palette)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Intensity
(0% Is Black)
0.0%
11.1%
20.0%
26.7%
33.3%
40.0%
44.4%
50.0%
55.6%
60.0%
66.6%
73.3%
80.0%
88.9%
100.0%
100.0%
Modulation Rate
(Ratio of ON to ON+OFF Pixels)
0
1/9
1/5
4/15
3/9
2/5
4/9
1/2
5/9
3/5
6/9
11/15
4/5
8/9
1
1
11.7.1.6 Output FIFO
The LCD controller contains a 19-entry x 16-bit wide output FIFO that is used to store pixel pin data
before it is driven out to the pins. Each time a modulated pixel value is output from the dither
generator, it is placed into a serial shifter. The size of the shifter is controlled by programming the
color/monochrome select and single- and dual-panel, double pixel data, and passive/active select bits
in the LCD’s control registers and the pixel bit size within palette entry 0 in the frame buffer. The
shifter can be configured to be 4, 8, or 16 bits wide. Four pins are used for single-panel monochrome
screens; 8 pins are used for single- and dual-panel monochrome screens as well as single-panel color
displays; 12 pins are used for active displays; and 16 pins are used for dual-panel color and active
displays. Once the correct number of pixels have been placed within the shifter (4-, 8-, or 16-pixel
values), the value is transferred to the top of the output FIFO. The value is then transferred down until
it reaches the last empty location within the FIFO. Each time a value is taken from the bottom of the
FIFO, the entry is invalidated and all data in the FIFO moves down one position.
SA-1110 Developer’s Manual
11-23