SA1110 Datasheet, PDF (92/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

System Control Module
9.3.6
9.4
9-22
This trim setting leaves an error of .16 cycles per 1023 seconds. The error calculation yields (in
parts-per-million or ppm):
Error = ^{0----.-1---6----c---y---c---l-e---s-}X----------1-----s--e---c---------- = 0.002 ppm
1023 sec 32768 cycles
Maximum Error Calculation Versus Real-Time Clock Accuracy
As seen from trim example #2, the maximum possible error approaches 1 clock per 2¹⁰-1 seconds.
Calculating the ppm error for this scenario yields:
Error (maximum) = ---1----c---y---c--l--e--- X----------1-----s--e---c---------- = 0.03 ppm
1023 sec 32768 cycles
To maintain an accuracy of +/- 5 seconds per month, the required accuracy is calculated to be:
Error = --5-----s--e---c-- X------1----m-----o---n---t--h------ = 1.9 ppm
month 2592000 sec
This calculation indicates that the accuracy of the SA-1110 trim mechanism is more than adequate
to compensate for the static environmental and manufacturing variables, and still provides
acceptable accuracy.
Real-Time Clock Register Locations
The following table describes the real-time clock registers.
Address
0h 9001 0000
0h 9001 0004
0h 9001 0008
0h 9001 0010
Name
RTAR
RCNR
RTTR
RTSR
Description
RTC alarm register
RTC count register
RTC timer trim register
RTC status register
Operating System Timer
The SA-1110 contains a 32-bit operating system timer that is clocked by the 3.6864-MHz oscillator.
The operating system count register (OSCR) is a free-running up-counter that is not cleared during
any reset (contains unknown value after reset). The OS timer also contains four 32-bit match registers
(OSMR 3:0). Each register can be written and read by the user. When the value in the OSCR matches
(is equal to) the value within any of the match registers, and the interrupt enable bit is set, the
corresponding bit in the OSSR is set. These bits are also routed to the interrupt controller where they
can be programmed to cause an interrupt. OSMR 3 also serves as a watchdog match register that
resets the SA-1110 when a match occurs. The only register that is reset to a known state is the
watchdog match enable register (WMER). The user must initialize all other registers and clear any set
status bits before the FIQ and IRQ interrupts are enabled within the CPU.
SA-1110 Developer’s Manual