SA1110 Datasheet, PDF (52/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Coprocessors
Function
Access data breakpoint address register (DBAR).
Access data breakpoint value register (DBVR).
Access data breakpoint mask register (DBMR).
Load data breakpoint control register (DBCR).
Write instruction breakpoint address and control register (IBCR).
OPC_2
0b000
0b000
0b000
0b000
0b000
CRm
0b0000
0b0001
0b0010
0b0011
0b1000
The DBCR register is a 3-bit register used to control the enabling and disabling of the data
breakpoints. Bits 0..2 are valid and positioned as shown below. Bits 3..31 are reserved. These bits
read as zeros and writes have no effect.
Data Breakpoint Control Register
(DBCR)
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
lw
Bits
0
1
2
31..3
Name
lw
saw
sdw
—
Load watch
0 – Disable load watch
1 – Enable load watch
Store address watch
0 – Disable store address watch
1 – Enable store address watch
Store data watch
0 – Disable store data watch
1 – Enable store data watch
Reserved.
Description
The IBCR is a write-only register used to load an address breakpoint address and to set an enable
bit for the function. If an address is loaded with bit 0 (E) set, then the address is enabled as a
breakpoint. If bit zero is cleared, then the breakpoint is disabled. Bit 1 is reserved and should be
written to zero.
5-8
SA-1110 Developer’s Manual