SA1110 Datasheet, PDF (244/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
control of the UDC’s pins to the PPC unit that configures them as inputs. Writes to reserved bits
should be zero.
0h 8000 0000
7
6
5
Reserved
SUSM
TIM
Reset
0
1
0
UDCCR
4
3
RIM
EIM
0
0
Read/Write and Read-Only
2
1
0
RESM
UDA
UDD
0
0
1
Bits
Name
Description
UDD disable.
0
UDD
0 – UDD enabled, UDC+ and UDC- used for USB serial transmission/reception.
1 – UDD disabled.
UDC active (read-only).
1
UDA
0 – UDC currently inactive.
1 – UDC currently active.
Resume interrupt mask.
2
RESM _{0 – Resume interrupt enabled..}
1 – Resume interrupt disabled.
Endpoint zero interrupt mask.
3
EIM
0 – Endpoint zero interrupt enabled.
1 – Endpoint zero interrupt disabled.
Receive interrupt mask.
4
RIM
0 – Receive interrupt enabled.
1 – Receive interrupt disabled.
Transmit interrupt mask.
5
TIM
0 – Transmit interrupt enabled.
1 – Transmit interrupt disabled.
Suspend interrupt mask.
6
SUSM _{0 – Suspend interrupt enabled.}
1 – Suspend interrupt disabled.
7
Reserved Reserved
The following subsections provide detailed descriptions of each bit in the UDC Control Register.
11.8.3.1
UDC Disable (UDD)
The UDC disable (UDD) bit is used to enable and disable the UDC. When UDD=0, the UDC is
enabled for serial transmission or reception. When UDC=1, it is disabled and the UDC+ and UDC-
pins are tristated.
If UDD is written to one the entire UDC design is reset. If this is done while the UDC is actively
transmitting or receiving data, it stops immediately and the remaining bits within the transmit or
receive serial shifter are reset. In addition, all entries within the transmit and receive FIFO ar reset.
11.8.3.2
UDC Active (UDA)
This read-only bit can be read to determine if the UDC is currently active. A one indicates that the
UDC is currently involved in a transaction.
11-64
SA-1110 Developer’s Manual