SA1110 Datasheet, PDF (50/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Coprocessors
5.2.9
5.2.10
Function
Flush D single entry
Clean Dcache entry
Drain write buffer
OPC_2
0b001
0b001
0b100
CRm
0b0110
0b1010
0b1010
Virtual address
Virtual address
Ignored
Data
Register 8 – TLB Operations
Register 8 is a write-only register. The CRm and OPC_2 fields are used to encode the following
TLB flush operations. Operation for all other values of OPC_2 and CRm is unpredictable.
Function
Flush I+D
Flush I
Flush D
Flush D single entry
OPC_2
0b000
0b000
0b000
0b001
CRm
0b0111
0b0101
0b0110
0b0110
Data
Ignored
Ignored
Ignored
Virtual address
Register 9 – Read-Buffer Operations
The read buffer is controlled and accessed through register 9 of coprocessor 15. The functions
supported are: flush-all buffers, flush-a-single entry, load-an-entry (1, 4 or 8 words), and
enable/disable user mode access.
The CRm and OPC_2 fields are used to encode these control operations. All other values for
OPC_2 and CRm are undefined and the results of using them are unpredictable.
Function
Flush all entries
Flush Buffer 0
Flush Buffer 1
Flush Buffer 2
Flush Buffer 3
Load Buffer 0 with one word
Load Buffer 0 with four words
Load Buffer 0 with eight words
Load Buffer 1 with one word
Load Buffer 1 with four words
Load Buffer 1 with eight words
Load Buffer 2 with one word
Load Buffer 2 with four words
Load Buffer 2 with eight words
Load Buffer 3 with one word
Load Buffer 3 with four words
OPC_2
0b000
0b001
0b001
0b001
0b001
0b010
0b010
0b010
0b010
0b010
0b010
0b010
0b010
0b010
0b010
0b010
CRm
0b0000
0b0000
0b0001
0b0010
0b0011
0b0000
0b0100
0b1000
0b0001
0b0101
0b1001
0b0010
0b0110
0b1010
0b0011
0b0111
Data
Ignored
Ignored
Ignored
Ignored
Ignored
Virtual address
Virtual address
Virtual address
Virtual address
Virtual address
Virtual address
Virtual address
Virtual address
Virtual address
Virtual address
Virtual address
5-6
SA-1110 Developer’s Manual