SA1110 Datasheet, PDF (107/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

System Control Module
9.5.7.3 Power Manager PLL Configuration Register (PPCR)
The PPCR contains bits used to configure the core operating frequency generated by the PLL. The
following table shows the bit-field definitions for this register. See Chapter 8, “Clocks” for the
frequencies generated through settings in this register. Note that the contents of this register are
preserved during sleep mode and do not need to be re-initialized after a wake-up event. The PPCR
is only cleared upon the assertion of nRESET (hard reset).
0h 9002 0014
PPCR
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
4..0
31..4
Name
CCF 4..0
—
Description
Clock speed configuration.
See Chapter 8, “Clocks” for the values in this field.
Reserved
9.5.7.4 Power Manager Wake-Up Enable Register (PWER)
The following table shows the location of all wake-up interrupt enable bits in the PWER. For a
GPIO to serve as a wake-up source, it must be programmed as an input in the GPDR. When a fault
condition is detected in the VDD_FAULT or BATT_FAULT pins, this register is set to hexadecimal
0000 0003, enabling only GP 1,0 as wake-up sources. This register is also set to this value on hard
reset (nRESET asserted). For reserved bits, writes are ignored and reads return zero.
.
0h 9002 000C
PWER
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bits
n
30..28
31
Name
WE n
—
WE31
Description
Sleep wake-up enable n (where n = 0 through 27).
0 – Wake-up due to GPIO n edge detect disabled.
1 – Wake-up due to GPIO n edge detect enabled.
Reserved
Sleep wake-up enable 31.
0 – Wake-up due to RTC alarm disabled.
1 – Wake-up due to RTC alarm enabled.
SA-1110 Developer’s Manual
9-37