SA1110 Datasheet, PDF (191/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.6.1.3
The RUN bit is the channel enable. It should be written to a one when the channel is ready for a
transfer. It can also be used to pause the channel in the middle of a transfer; when it is set to a one
again, the channel will resume from the current pointer value using the current active buffer. If the
RUN bit is cleared in the middle of a burst, the burst will complete before the channel is paused.
The DDAR may be written only when RUN is zero.
The IE bit is the interrupt enable for the channel. An interrupt is generated if the DONEA,
DONEB, or ERROR bits are set and the IE bit is set. The interrupt is negated when all of these
status bits are cleared.
The ERROR bit is set if the DMA controller is incorrectly programmed and points to reserved
memory space. No error is generated for references to nonexistent external memory. If enabled,
ERROR generates a channel interrupt.
The DONEA bit is a status bit set by the DMA controller to indicate that the transfer to or from
buffer A has completed. If enabled, DONEA causes a channel interrupt.
The STRTA bit is written by the user to start the channel transfer to or from buffer A. When
DONEA is set, STRTA is cleared. The immediate action resulting from setting STRTA is
dependent on the state of the BIU bit.
The DONEB bit is a status bit set by the DMA controller to indicate that the transfer to or from
buffer B has completed. If enabled, DONEB will cause a channel interrupt.
The STRTB bit is written by the user to start the channel transfer to or from buffer B. When
DONEB is set, STRTB is cleared. The immediate action resulting from setting STRTB is
dependent on the state of the BIU bit.
The BIU bit indicates the current buffer-in-use (A or B). If BIU is a zero, buffer A is in use. If BIU
is a one, buffer B is in use.The setting of DONEA or DONEB toggles the BIU bit. This bit is never
cleared except on reset (either hardware, software, or sleep). For this reason, the processor must
interrogate this bit before programming the channel for a new transfer. If both STRTA and STRTB
are set at the same time, the first buffer serviced depends on the state of BIU.
DMA Buffer A Start Address Register (DBSAn)
The DBSAn is a 32-bit read/write register that contains the starting memory address for buffer A.
This register may be written only when STRTA is zero.
SA-1110 Developer’s Manual
11-11