SA1110 Datasheet, PDF (68/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Clocks
8.1
Intel^® StrongARM SA-1110 Crystal Oscillators
The SA-1110 clocks are derived from two crystals connected to on–chip oscillators. The first clock
source is a 3.6864-MHz crystal that feeds the CPU PLL and the 48-MHz PLL. The CPU PLL
multiplies the oscillator output up to the core frequency. This frequency is then divided down to
generate baud rates for the serial ports. If the UARTs are not being used or do not need standard
baud rates, then the 3.6864 -Hz oscillator may be replaced with a 3.5795-MHz crystal to generate
frequencies as shown in Table 8-1.The second oscillator is connected to a 32.768-kHz crystal. The
output of this oscillator clocks the power management controller and the real-time clock (RTC).
See Appendix B, “3.6864–MHz Oscillator Specifications” and Appendix C, “32.768–kHz
Oscillator Specifications” for detailed specifications of the crystal oscillators.
8.2
Core Clock Configuration Register
Table 8-1.
The core clock frequency is configured by software through the core clock configuration field
(CCF 4:0) in the power manager phase-locked loop (PLL) configuration register (PPCR). This
field should be programmed during the boot sequence for the desired full-speed operation.
nRESET clears the field by selecting the lowest frequency operation.
See Section 9.5, “Power Manager” on page 9-26 for the physical address used to access this
register.
Table 8-1 shows the core clock frequency as a function of the CCF setting.
Core Clock Configurations
CCF 4:0
Core Clock Frequency in MHz
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100– 11111
3.6864-MHz Crystal Oscillator
59.0
73.7
88.5
103.2
118.0
132.7
147.5
162.2
176.9
191.7
206.4
221.2
Not supported.
3.5795-MHz Crystal Oscillator
57.3
71.6
85.9
100.2
114.5
128.9
143.2
157.5
171.8
186.1
200.5
214.8
—
The actual core clock (DCLK) can switch between being driven by the high speed core clock
(CCLK, set by CCF 4:0) and the memory clock (MCLK), which runs at half the frequency of
CCLK. CCLK is used except when the SA-1110 is waiting for fills to complete after a cache miss.
8-2
SA-1110 Developer’s Manual