SA1110 Datasheet, PDF (246/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.8.3.8 Software Control of the UDC
When an interrupt occurs and the Interrupt Service Routine is entered, read the ICPR, ICIP, or
ICFP registers to determine which interrupts occurred. If bit 13, UDC service request, is set, then
read the UDC Statue/Interrupt Register (UDCSR) in the UDC unit to determine which UDC
interrupt caused the request. Based on which interrupt is set, do the following:
1. Wake-up or GPIOn Interrupt
a. After wake-up or a GPIOn interrupt, software should read the GPIOn pin
b. If a read of GPIOn is 0, then the USB cable is not connected and wake-up was due to
some other occurrence.
c. If a read of GPIOn equals 1, then the USB cable was connected. Initialize the UDC and
clear the SUSM bit.
Note: If GPIOn is shared with some other device that can wake the part, you may need to disconnect and
then reconnect the USB cable in order to synchronize to the PC.
2. Reset Interrupt
a. Software should write a 1 to the RSTIR bit of the UDCSR to clear the reset interrupt.
b. If a read of GPIOn is 0, the USB cable has been disconnected, and the part can be put into
sleep mode.
c. If a read of GPIOn is 1, then software attempts to write a 0 to the SUSM bit of the
UDCCR attempting to unmask the suspend interrupt.
1. If software is able to clear this bit, then the interrupt was due to the reset being negated.
Software should be able to initialize any required variables and registers.
2. If software is unable to clear this bit, the interrupt was due to reset being asserted.
Return to main.
3. Suspend Interrupt
a. Software should be able to write a 1 to the SUSM bit of the UDCCR masking any further
suspend interrupts.
b. Software should be able to write a 1 to the SUSIR bit of the UDCSR clearing the suspend
interrupt.
4. Resume Interrupt
a. Software should be able to write a 1 then a 0 to the RESM bit of the UDCCR clearing the
internal suspend state machine.
b. Software may also write a 0 to the SUSM bit of the UDCCR to unmask the suspend
interrupt.
c. Software should be able to write a 1 to the RESIR bit of the UDCSR clearing the resume
interrupt.
5. EndPoint0 Interrupt
a. Get the command packet from the FIFO.
b. Parse the command.
c. Setup the endpoint to respond to the command
6. EndPoint1 Interrupt
a. Check that a complete packet is received.
b. Check for any errors.
11-66
SA-1110 Developer’s Manual