SA1110 Datasheet, PDF (46/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Coprocessors
5.2
Coprocessor 15 Definition
Table 5-1.
The SA-1110 coprocessor 15 contains registers that control the cache, MMU, and write buffer
operation as well as some clocking functions. These registers are accessed using CPRT instructions
to coprocessor 15 with the processor in any privileged mode. Only some of registers 0–15 are
valid; the result of an access to an invalid register is unpredictable. Table 5-1 lists the coprocessor
15 control registers.
Cache and MMU Control Registers (Coprocessor 15)
Register
0
1
2
3
4
5
6
7
8
9
10..12
13
14
15
Register Reads
ID
Control
Translation table base
Domain access control
RESERVED
Fault status
Fault address
RESERVED
RESERVED
RESERVED
RESERVED
Read process ID (PID)
Read breakpoint
RESERVED
Register Writes
RESERVED
Control
Translation table base
Domain access control
RESERVED
Fault status
Fault address
Cache operations
TLB operations
Read buffer operations
RESERVED
Write process ID (PID)
Write breakpoint
Test, clock, and idle
5.2.1 Register 0 – ID
Register 0 is a read-only register that returns an architecture and implementation-defined
identification for the device.
Register 0 – ID
Read-Only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
69
Architecture Version
Part Number
Stepping
Architecture Version ARM architecture version
01 = Version 4
Part Number
Part number
B11 = SA1110
Stepping
Stepping revision of SA-1110
0000 = A0 stepping 0100 = B0 stepping
0110 = B2 stepping 1000 = B4 stepping
0101 = B1 stepping
5-2
SA-1110 Developer’s Manual