SA1110 Datasheet, PDF (17/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

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11-37
13-1
13-2
13-3
14-1
16-1
16-2
16-3
16-4
16-5
MPC/Codec Sampling Counter Synchronization.........................................11–129
Audio/Telecom Transmit/Receive FIFO Data Format .................................11–131
Texas Instruments* Synchronous Serial Frame Format .............................11–152
Motorola* SPI Frame Format ......................................................................11–153
National Microwire* Frame Format..............................................................11–154
Transmit/Receive FIFO Data Format ..........................................................11–155
Motorola* SPI Frame Formats for SPO and SPH Programming.................11–161
Memory Bus AC Timing Definitions.................................................................13–2
LCD AC Timing Definitions..............................................................................13–3
MCP AC Timing Definitions............................................................................. 13–3
SA-1110 256-Pin mBGA Mechanical Drawing ................................................ 14–2
Test Access Port (TAP) Controller State Transitions ...................................... 16–1
Boundary-Scan Block Diagram ....................................................................... 16–5
Boundary-Scan General Timing ...................................................................... 16–7
Boundary-Scan Tristate Timing....................................................................... 16–8
Boundary-Scan Reset Timing ......................................................................... 16–8
Tables
1-1
1-2
1-3
1-4
2-1
3-1
4-1
5-1
6-1
7-1
8-1
9-1
9-2
9-3
9-4
9-5
10-1
10-2
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10-9
10-10
11-1
11-2
11-3
11-4
Features of the SA-1110 CPU...........................................................................1–2
Changes to the SA-1110 Core from the SA-110 ...............................................1–2
Feature Additions to the SA-1110 from the SA-110 ..........................................1–3
Feature Additions to the SA-1110 from the SA-1100 ........................................1–3
Signal Descriptions (Sheet 1 of 4).....................................................................2–4
Vector Summary................................................................................................3–4
Instruction Timing ..............................................................................................4–1
Cache and MMU Control Registers (Coprocessor 15)......................................5–2
Effects of the Cacheable and Bufferable Bits on the Data Caches ...................6–3
Valid MMU, Dcache, and Write Buffer Combinations........................................7–2
Core Clock Configurations ................................................................................8–2
OS Timer Register Locations .......................................................................... 9–26
SA-1110 Power and Clock Supply Sources and States During
Power-Down Modes ........................................................................................ 9–33
Pin State During Sleep ................................................................................... 9–34
Power Manager Register Locations ................................................................ 9–41
Reset Controller Register Locations................................................................ 9–44
SA-1110 Transactions.....................................................................................10–8
Memory Interface Control Registers................................................................ 10–9
Timing Interpretations of Possible SDRAM/SMROM MDCAS Settings ........ 10–20
BS_xx Bit Encoding....................................................................................... 10–24
BCLK Speeds for 160-MHz Processor Core Frequency ...............................10–24
Some DRAM Memory Size Options .............................................................. 10–29
DRAM or SMROM Row/Column Address Multiplexing ................................. 10–30
SDRAM Command Encoding........................................................................ 10–34
Summary of Static Memory and Variable Latency I/O Capabilities............... 10–42
SMROM Command Encoding ....................................................................... 10–52
Peripheral Control Modules’ Register Width and DMA Port Size....................11–2
Peripheral Unit Base Addresses ..................................................................... 11–3
Peripheral Unit Interrupt Numbers................................................................... 11–3
Dedicated Peripheral Pins............................................................................... 11–4
SA-1110 Developer’s Manual
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