SA1110 Datasheet, PDF (123/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
10.2 Memory Configuration Registers
The SA-1110 memory interface is programmed through a set of configuration registers that are
described in the following sections. Many timing parameters are encoded as a number of memory
clock cycles, where each memory clock cycle is equivalent to two CPU clock cycles.
Table 10-2 shows the registers associated with the memory interface and the physical addresses
used to access them. All addressing is little endian. These registers are readable and writable only
as full words. They are grouped together within one page and thus all have the same memory
protections.
Table 10-2. Memory Interface Control Registers
Physical Address
0xA000 0000
0xA000 0004
0xA000 0008
0xA000 000C
0xA000 0010
0xA000 0014
0xA000 0018
0xA000 001C
0xA000 0020
0xA000 0024
0xA000 0028
0xA000 002C
0xA000 0030
Symbol
MDCNFG
MDCAS00
MDCAS01
MDCAS02
MSC0
MSC1
MECR
MDREFR
MDCAS20
MDCAS21
MDCAS22
MSC2
SMCNFG
Register Name
DRAM configuration register
CAS waveform rotate register 0 for DRAM bank
pair 0/1
CAS waveform rotate register 1 for DRAM bank
pair 0/1
CAS waveform rotate register 2 for DRAM bank
pair 0/1
Static memory control register 0
Static memory control register 1
Expansion memory (PCMCIA) bus configuration
register
DRAM refresh control register
CAS waveform rotate register 0 for DRAM bank
pair 2/3
CAS waveform rotate register 1 for DRAM bank
pair 2/3
CAS waveform rotate register 2 for DRAM bank
pair 2/3
Static memory control register 2
SMROM configuration register
Note: A question mark (?) signifies that the Reset value of that bit is undefined when the processor has
completed its reset cycle.
SA-1110 Developer’s Manual
10-9