SA1110 Datasheet, PDF (248/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.8.6 UDC IN Max Packet Register
Reset
The UDC IN max packet register holds the value of the number of bytes the UDC core is to
transmit minus one. This is done in order to accommodate maximum packets of 256 bytes, without
going to a max packet field of more than 8 bits. In order to transmit packets of 256 bytes, a value of
0xff (255) should be written into the IN max packet register. At reset the IN max packet register
contains 0x08, and will therefore transmit packets of length 9 bytes.
0h 8000 000C
UDCIMP
Read/Write
7
6
5
4
3
2
1
0
Max Packet Size - 1
0
0
0
0
1
0
0
0
Bits
Name
Description
IN max packet size.
7..0
IN MaxP
8-bit field containing the value of the number of bytes to transmit minus one.
11.8.7
11.8.7.1
11.8.7.2
11.8.7.3
11.8.7.4
UDC Endpoint 0 Control/Status Register
The UDC endpoint zero control/status register contains 8 bits that are used to operate endpoint zero
(control endpoint).
OUT Packet Ready (OPR)
The OUT packet ready bit is set by the UDC when it receives a valid token to endpoint zero. When
this bit is set, the EIR bit will be set in the UDC status/interrupt register if endpoint zero interrupts
are enabled. This bit is cleared by writing a one to the serviced out packet ready bit (6). The UDC
is not allowed to enter the data phase of a transaction until this bit is cleared. If there is no data
phase, then the CPU should set the data end bit (4) at the same time it clears this bit.
IN Packet Ready (IPR)
The IN packet ready bit is set by the CPU after it has written a packet to the endpoint zero FIFO to
be transmitted. The UDC will automatically clear this bit when the packet has been successfully
transmitted. When this bit is cleared, the EIR bit in the UDC status/interrupt register will be set if
endpoint zero interrupts are enabled. The CPU will not be able to clear this bit.
Sent Stall (SST)
The sent stall bit is set by the UDC when it must abort the current control transfer by issuing a
STALL handshake due to a protocol violation. When this bit is set, the EIR bit in the UDC
status/interrupt register will be set if endpoint zero interrupts are enabled. The CPU clears this bit
by writing a one to it.
Force Stall (FST)
The force stall bit can be set by the UDC to force the UDC to issue a STALL handshake. The UDC
issues a STALL handshake for the current setup control transfer and the bit is cleared by the UDC
because endpoint zero cannot remain in a stalled condition.
11-68
SA-1110 Developer’s Manual