SA1110 Datasheet, PDF (187/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.6.1.1
DMA Device Address Register (DDARn)
The DDARn is a 32-bit read/write register containing channel information regarding the target
device. Writes to this register are blocked if the RUN bit in the DCSRn is one. The following figure
shows the format for this register; question marks indicate that the values are unknown at reset.
DDARn
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
Bits
0
1
2
3
7..4
31..8
Name
RW
E
BS
DW
DS 3..0
DA 31..8
Description
Device data transfer direction (read/write).
0 = Transfer is a write (memory to device).
1 = Transfer is a read (device to memory).
Device endianess.
0 = Byte ordering is little endian.
1 = Byte ordering is big endian.
Device burst size.
0 = Four datums per burst.
1 = Eight datums per burst.
Device datum width.
0 = Datum size is one byte.
1 = Datum size is one half-word.
Device select.
This field is programmed to point to the desired device.
Device address field.
This field is a partial address of the data port of the device currently being serviced. ¹
1 _{“Partial” means that certain bits in the address are assumed to be zero. The DA 31:8 field is constructed as follows:}
DA 31:28 = Device port address 31:28.
Device port address 27:22 is assumed to be zero.
DA 27:8 = Device port address 21:2.
Device port address 1:0 is assumed to be zero.
SA-1110 Developer’s Manual
11-7