SA1110 Datasheet, PDF (45/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Coprocessors
5
The operation and configuration of the Intel^® StrongARM^* SA-1110 Microprocessor (SA-1110) is
controlled with coprocessor instructions, configuration pins, and memory-management page
tables. The coprocessor 15 instructions manipulate on-chip registers that control the configuration
of the cache, write buffer, MMU, read buffer, breakpoints, and other configuration options.
Note: The gray areas in the register and translation diagrams are reserved and should be programmed 0
for future compatibility.
5.1
Internal Coprocessor Instructions
The on-chip cache, MMU, write buffer, and read buffers are controlled using MRC instructions and
MCR instructions. These operations to coprocessor 15 are allowed only in nonuser modes except
when read-buffer operations are explicitly enabled. The undefined instruction trap is taken if
accesses are attempted in user mode. Figure 5-1 shows the format of internal coprocessor
instructions MRC and MCR.
Figure 5-1. Format of Internal Coprocessor Instructions MRC and MCR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Cond
1110
n
CRn
Rd
1 1 1 1 OPC_2 1
CRm
Cond
n
CRn
Rd
OPC_2
CRm
ARM^* condition codes
1 MRC register read
0 MCR register write
SA-1110 register
ARM register
Function bits for some MRC/MCR instructions
Function bits for some MRC/MCR instructions
* Other brands and names are the property of their respective owners.
SA-1110 Developer’s Manual
5-1