SA1110 Datasheet, PDF (15/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

or PEXTAL and VSS ............................................................................ B–2
B.1.1.3 Parasitic Resistance Between PXTAL and PEXTAL ........................... B–2
B.1.1.4 Parasitic Resistance Between PXTAL or PEXTAL
and VSS ............................................................................................... B–2
B.1.2 Quartz Crystal Specification ......................................................................... B–3
C
32.768–KHz Oscillator Specifications ....................................................................... C–1
C.1 Specifications ................................................................................................... C–1
C.1.1 System Specifications .................................................................................. C–1
C.1.1.1 Temperature Range ............................................................................. C–1
C.1.1.2 Current Consumption ........................................................................... C–1
C.1.1.3 Startup Time......................................................................................... C–1
C.1.1.4 Frequency Shift Due to Temperature Effect on the Circuit .................. C–2
C.1.1.5 Parasitic Capacitance Off-chip Between TXTAL
and TEXTAL......................................................................................... C–2
C.1.1.6 Parasitic Capacitance Off-chip Between TXTAL
or TEXTAL and VSS ............................................................................ C–2
C.1.1.7 Parasitic Resistance Between TXTAL and TEXTAL............................ C–2
C.1.1.8 Parasitic Resistance Between TXTAL or TEXTAL
and VSS ............................................................................................... C–2
C.1.2 Quartz Crystal Specification ......................................................................... C–3
D
Internal Test ................................................................................................................. D–1
D.1 Test Unit Control Register (TUCR)................................................................... D–1
Figures
1-1
1-2
2-1
2-2
2-3
5-1
8-1
9-1
9-2
9-3
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
SA-1110 Features .............................................................................................1–1
SA-1110 Example System ................................................................................1–5
SA-1110 Block Diagram ....................................................................................2–2
SA-1110 Functional Diagram ............................................................................2–3
SA-1110 Memory Map ......................................................................................2–9
Format of Internal Coprocessor Instructions MRC and MCR............................5–1
SA-1110 Clock System Block Diagram .............................................................8–1
General-Purpose I/O Block Diagram.................................................................9–2
Interrupt Controller Block Diagram .................................................................. 9–11
Transitions Between Modes of Operation ....................................................... 9–32
General Memory Interface Configuration ........................................................ 10–1
DRAM System Example.................................................................................. 10–4
SDRAM System Example ............................................................................... 10–5
SMROM System Example............................................................................... 10–6
DRAM Single-Beat Transactions................................................................... 10–32
Dram Burst-of-Eight Transactions ................................................................. 10–33
SDRAM State Machine ................................................................................. 10–36
SDRAM 1-Beat Read/Write/Read Timing for 4 Bank x 4 M x 4 Bit
Organization (64 Mbit)...................................................................................10–37
SDRAM 1-Beat Read/Write Timing for 4 Bank x 4 M x 4 Bit Organization
(64 Mbit) at Half-Memory Clock Frequency (MDREFR:KnDB2=1)) .............. 10–38
SA-1110 Developer’s Manual
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