SA1110 Datasheet, PDF (234/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
Figure 11-14. Active Mode Pixel Clock and Data Pin Timing
L_FCLK
(VSYNC)
L_BIAS
OE)
L_LCLK
(HSYNC)
L_PCLK
LDD[7:0],
GPIO[9:2]
PCP = 1
Data Pins Sampled
by the Display
Pixel 0
Pixel 1
Data Pins Change
Pixel 2
Pixel 3
Notes:
PCP - Pixel clock polarity:
0 - Pixels driven from data pins on rising edge of pixel clock.
1 - Pixels driven from data pins on falling edge of pixel clock.
A8099-01
11-54
SA-1110 Developer’s Manual