MEC1322 Datasheet, PDF (98/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
5.11.7 BAR INHIBIT REGISTER
Offset ^20h
Bits
Description
31:0 BAR_Inhibit[31:0]
When bit Di of BAR_Inhibit is 1, the BAR for Logical Device i is dis-
abled and its addresses will not be claimed on the LPC bus, inde-
pendent of the value of the Valid bit in the BAR.The association
between bits in BAR_Inhibit and Logical Devices is illustrated in
Table 5-22, "BAR Inhibit Device Map".
Type
R/W
TABLE 5-22: BAR INHIBIT DEVICE MAP
Bar Inhibit Bit
Logical Device Number
0
0h
1
1h
.
.
.
.
.
.
31
31h
5.11.8 LPC BAR INIT REGISTER
Offset ^30h
Bits
Description
Type
15:0 BAR_Init
R/W
This field is loaded into the LPC BAR at offset 60h on nSIO_RESET.
Default
0h
Reset
Event
VCC1_R
ESET
Default
002Eh
Reset
Event
nSIO_R
ESET
DS00001719D-page 98
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